KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 5

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SPI Interface to I/O Registers............................................................................................................................................. 33
Register Map: MAC, PHY and QMU................................................................................................................................... 40
August 2009
Micrel, Inc.
EEPROM Interface ......................................................................................................................................................... 31
Loopback Support........................................................................................................................................................... 32
I/O Registers................................................................................................................................................................... 33
Internal I/O Registers Space Mapping............................................................................................................................ 34
Bit Type Definition........................................................................................................................................................... 40
0x00 – 0x07: Reserved................................................................................................................................................... 40
Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................................... 40
0x0A – 0x0F: Reserved .................................................................................................................................................. 40
Host MAC Address Registers: MARL, MARM and MARH ............................................................................................. 40
Host MAC Address Register Low (0x10 – 0x11): MARL................................................................................................ 41
Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................................... 41
Host MAC Address Register High (0x14 – 0x15): MARH .............................................................................................. 41
0x16 – 0x1F: Reserved .................................................................................................................................................. 41
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................... 41
EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................................... 42
Memory BIST Info Register (0x24 – 0x25): MBIR .......................................................................................................... 42
Global Reset Register (0x26 – 0x27): GRR ................................................................................................................... 43
0x28 – 0x29: Reserved................................................................................................................................................... 43
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................... 43
0x2C – 0x2F: Reserved .................................................................................................................................................. 43
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ........................................................................................ 43
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ........................................................................................ 44
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 ................................................................................ 44
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 ................................................................................ 44
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 ................................................................................ 44
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3................................................................................ 44
0x3C – 0x3F: Reserved .................................................................................................................................................. 45
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ........................................................................................ 45
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ........................................................................................ 45
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 ................................................................................ 45
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 ................................................................................ 45
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 ................................................................................ 45
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3................................................................................ 45
0x4C – 0x4F: Reserved .................................................................................................................................................. 46
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ........................................................................................ 46
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ........................................................................................ 46
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 ................................................................................ 46
Driver Routine for Transmit Packet from Host Processor to KSZ8851SNL............................................................. 26
Receive Queue (RXQ) Frame Format ..................................................................................................................... 29
Frame Receiving Path Operation in RXQ ................................................................................................................ 29
Driver Routine for Receive Packet from KSZ8851SNL to Host Processor.............................................................. 30
Near-end (Remote) Loopback.................................................................................................................................. 32
Far-end (Local) Loopback ........................................................................................................................................ 32
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KSZ8851SNL/SNLI
M9999-083109-2.0