KSZ8851SNLI Micrel Inc, KSZ8851SNLI Datasheet - Page 26

• Manufacturer Part Number: KSZ8851SNLI
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNLI

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Driver Routine for Transmit Packet from Host Processor to KSZ8851SNL
The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller. It is
user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while
transmitting the frame, it’s the user’s choice to decide whether the driver should attempt to retransmit the same frame or
discard the data. The following Figures 11 and 12 shows the step-by-step for single and multiple transmit packets from
host processor to KSZ8851SNL.
August 2009
Micrel, Inc.
Register Name
[bit](offset)
TXCR[3:0](0x70)
TXCR[8:5](0x70)
TXMIR[12:0](0x78)
TXQCR[0](0x80)
TXQCR[1](0x80)
TXQCR[2](0x80)
RXQCR[3](0x82)
TXFDPR[14](0x84)
IER[14][6](0x90)
ISR[15:0](0x92)
TXNTFSR[15:0](0x9E)
Description
Set transmit control function as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
The amount of free transmit memory available is represented in units of byte. The TXQ memory (6 KByte)
is used for both frame payload and control word.
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851SNL will enable current TX
frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before setting up another new TX frame.
When this bit is written as 1, the KSZ8851SNL will generate interrupt (bit 6 in ISR register) to CPU when
TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR
(0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before set to 1 again
For multiple frames to transmit, set this bit 2 = 1 (auto-enqueue). the KSZ8851SNL will enable current all
TX frames prepared in the TX buffer are queued to transmit automatically.
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame)
Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to the
data register.
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit frames size in double-word count.
Table 9. Registers Setting for Transmit Function Block
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KSZ8851SNL/SNLI
M9999-083109-2.0