S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 84

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output Control
6.6.1.3
6.6.1.4
84
PTAPE[7:5,
PTASE[7:5,
Reserved
Reserved
Reset:
Reset:
7:5,3:0
7:5,3:0
Field
Field
3:0]
3:0]
5:4
5:4
W
W
R
R
PTAPE7
PTASE7
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Port A Pull Enable Register (PTAPE)
0
Port A Slew Rate Enable Register (PTASE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured to detect
rising edges.
PTAPE6
PTASE6
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
0
0
6
6
Table 6-4. PTAPE Register Field Descriptions
Table 6-5. PTASE Register Field Descriptions
R
R
0
0
5
5
MC9S08SG32 Data Sheet, Rev. 8
NOTE
R
R
0
0
4
4
Description
Description
PTAPE3
PTASE3
3
0
3
0
PTAPE2
PTASE2
0
0
2
2
PTAPE1
PTASE1
Freescale Semiconductor
0
0
1
1
PTAPE0
PTASE0
0
0
0
0