S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 316

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
316
1
2
3
4
5
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of t
frequency changes to the untrimmed DCO frequency (f
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
2
3
4
5
6
C
D
D
D
D
D
C
Control Timing
Bus frequency
(t
Internal low power
oscillator period
External reset pulse width
Reset low drive
Pin interrupt pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
cyc
= 1/f
Bus
)
3
Rating
disabled (PTxSE = 0)
disabled (PTxSE = 0)
2
enabled (PTxSE = 1)
enabled (PTxSE = 1)
DD
Asynchronous path
Synchronous path
and 80% V
MC9S08SG32 Data Sheet, Rev. 8
Slew rate control
Slew rate control
Slew rate control
Slew rate control
Table A-13. Control Timing
-40 C to 125 C
-40 C to 125 C
> 125 C
> 125 C
DD
DD
reset
levels. Temperature range –40°C to 125°C.
5
= 5.0V, 25°C unless otherwise stated.
5
2
4
= (f
dco_ut
t
t
t
t
Symbol
ILIH,
Rise
Rise
Rise
t
t
t
rstdrv
f
extrst
LPO
Bus
, t
, t
, t
t
)/4) because TRIM is reset to 0x80 and FTRIM is reset
IHIL
Fall
Fall
Fall
1.5 x t
66 x t
Min
700
600
100
100
dc
dc
—
—
—
—
cyc
cyc
Typ
cyc
—
—
—
40
75
11
35
. After POR reset, the bus clock
1
1500
1500
Max
Freescale Semiconductor
20
18
—
—
—
—
—
—
—
MHz
MHz
Unit
μs
μs
ns
ns
ns
ns
ns
♦
—
♦
—
♦
♦
♦
♦
♦
♦
♦
Rated
Temp
—
♦
—
♦
♦
♦
♦
♦
♦
♦
♦