S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 176

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 11 Internal Clock Source (S08ICSV2)
11.3.1
176
IREFSTEN
IRCLKEN
IREFS
CLKS
Field
RDIV
7:6
5:3
2
1
0
Reset:
W
R
ICS Control Register 1 (ICSC1)
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
00
01
10
11
Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits.
Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.
000 Encoding 0 — Divides reference clock by 1 (reset default)
001 Encoding 1 — Divides reference clock by 2
010 Encoding 2 — Divides reference clock by 4
011 Encoding 3 — Divides reference clock by 8
100 Encoding 4 — Divides reference clock by 16
101 Encoding 5 — Divides reference clock by 32
110 Encoding 6 — Divides reference clock by 64
111 Encoding 7 — Divides reference clock by 128
Internal Reference Select — The IREFS bit selects the reference clock source for the FLL.
1 Internal reference clock selected
0 External reference clock selected
Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as
ICSIRCLK.
1 ICSIRCLK active
0 ICSIRCLK inactive
Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock
remains enabled when the ICS enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before
0 Internal reference clock is disabled in stop
entering stop
Output of FLL is selected.
Internal reference clock is selected.
External reference clock is selected.
Reserved, defaults to 00.
7
0
CLKS
Table 11-2. ICS Control Register 1 Field Descriptions
0
6
Figure 11-3. ICS Control Register 1 (ICSC1)
MC9S08SG32 Data Sheet, Rev. 8
0
5
RDIV
0
4
Description
0
3
IREFS
1
2
IRCLKEN
Freescale Semiconductor
0
1
IREFSTEN
0
0