S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 135

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

9.3.8
The pin control registers disable the digital interface to the associated MCU pins used as analog inputs to
reduce digital noise and improve conversion accuracy. APCTL1 controls the pins associated with channels
0–7 of the ADC module.
Some MCUs may not use all bits implemented in this register. Bits in this register that do not have
associated external analog inputs have no control function. Consult the ADC channel assignment in the
module introduction.
Freescale Semiconductor
ADPC7
ADPC6
ADPC5
ADPC4
ADPC3
ADPC2
Field
7
6
5
4
3
2
Reset:
W
R
Pin Control 1 Register (APCTL1)
ADC Pin Control 7 — ADPC7 controls the pin associated with channel AD7.
0 AD7 pin I/O control enabled
1 AD7 pin I/O control disabled
ADC Pin Control 6 — ADPC6 controls the pin associated with channel AD6.
0 AD6 pin I/O control enabled
1 AD6 pin I/O control disabled
ADC Pin Control 5 — ADPC5 controls the pin associated with channel AD5.
0 AD5 pin I/O control enabled
1 AD5 pin I/O control disabled
ADC Pin Control 4 — ADPC4 controls the pin associated with channel AD4.
0 AD4 pin I/O control enabled
1 AD4 pin I/O control disabled
ADC Pin Control 3 — ADPC3 controls the pin associated with channel AD3.
0 AD3 pin I/O control enabled
1 AD3 pin I/O control disabled
ADC Pin Control 2 — ADPC2 controls the pin associated with channel AD2.
0 AD2 pin I/O control enabled
1 AD2 pin I/O control disabled
ADPC7
7
0
ADICLK
00
01
10
11
ADPC6
0
Table 9-10. APCTL1 Register Field Descriptions
6
Figure 9-10. Pin Control 1 Register (APCTL1)
Bus clock
Bus clock divided by 2
Alternate clock (ALTCLK)
Asynchronous clock (ADACK)
ADPC5
MC9S08SG32 Data Sheet, Rev. 8
Table 9-9. Input Clock Select
0
5
ADPC4
Selected Clock Source
0
4
Description
ADPC3
0
3
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
ADPC2
0
2
ADPC1
0
1
ADPC0
0
0
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