S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 74

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 5 Resets, Interrupts, and General System Control
5.7.7
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU. This register should be written during the user’s reset initialization program to set
the desired controls even if the desired settings are the same as the reset settings
74
1
2
Any other Reset:
Power-on Reset:
PPDACK
This bit can be written only one time after power-on reset. Additional writes are ignored.
This bit can be written only one time after reset. Additional writes are ignored.
PPDC
LVWV
PPDF
Field
LVDV
LVD Reset:
5
4
3
2
0
System Power Management Status and Control 2 Register
(SPMSC2)
Low-Voltage Detect Voltage Select — This write-once bit selects the low voltage detect (LVD) trip point setting.
It also selects the warning voltage range. See
Low-Voltage Warning Voltage Select — This bit selects the low voltage warning (LVW) trip point voltage. See
Table
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit
Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
W
R
5-11.
0
7
0
0
0
= Unimplemented or Reserved
Table 5-10. SPMSC2 Register Field Descriptions
0
0
0
0
6
MC9S08SG32 Data Sheet, Rev. 8
LVDV
0
u
u
5
1
LVWV
Table
u
4
0
u
Description
5-11.
PPDF
0
0
0
3
PPDACK
u = Unaffected by reset
0
0
0
0
2
es
Freescale Semiconductor
0
0
0
0
1
PPDC
0
0
0
0
2