S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 61

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 5
Resets, Interrupts, and General System Control
5.1
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt
in the MC9S08SG32 Series. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this data sheet. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog are not part of on-chip peripheral systems with their own chapters.
5.2
Reset and interrupt features include:
5.3
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08SG32 Series has the following sources for reset:
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).
Freescale Semiconductor
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Multiple sources of reset for flexible system configuration and reliable operation
System reset status register (SRS) to indicate source of most recent reset
Separate interrupt vector for each module (reduces polling overhead) (see
Power-on reset (POR)
External pin reset (PIN)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect (ILOP)
Illegal address detect (ILAD) - any address in memory map that is listed as unimplemented will
produce an illegal address reset
Background debug forced reset
Introduction
Features
MCU Reset
MC9S08SG32 Data Sheet, Rev. 8
Table
5-2)
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