S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 180
S9S08SG16E1CTJ
Manufacturer Part Number
S9S08SG16E1CTJ
Description
Manufacturer
Freescale
Datasheet
1.S9S08SG16E1CTJ.pdf
(330 pages)
Specifications of S9S08SG16E1CTJ
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
16
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
16KB
Lead Free Status / RoHS Status
Compliant
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Chapter 11 Internal Clock Source (S08ICSV2)
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 1024 times the reference frequency,
as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal
reference clock is enabled.
11.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock.The FLL loop will lock the frequency to 1024 times the reference frequency,
as selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external
reference clock is enabled.
11.4.1.3
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 1024
times the reference frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC
communications, and the internal reference clock is enabled.
11.4.1.4
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
180
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CLKS bits are written to 00
IREFS bit is written to 1
RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
CLKS bits are written to 00
IREFS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is active or LP bit is written to 0
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is not active and LP bit is written to 1
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
FLL Bypassed Internal Low Power (FBILP)
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor
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