NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 392

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Notes:
1.
2.
3.
4.
5.
6.
7.
8.
6.2.2
Table 6-5.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
396
V
V
V
V
I
I
I
R
GTLREF
R
OL
LI
LO
IL
IH
OL
OH
on
TT
Symbol
Refer to chapter 5 of Intel
(EDS) Addendum.
Crossing voltage is defined as the instantaneous voltage when the rising edge of CORECLKP is equal to the falling edge of
CORECLKN.
Overshoot is defined as the absolute value of the maximum voltage.
Undershoot is defined as the absolute value of the minimum voltage.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback. Both maximum Rising and Falling Ringbacks should not cross the threshold region.
Threshold Region is defined as a region centered around the crossing point voltage in which the differential receiver switches.
It includes input threshold hysteresis.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
VHavg (the average of V
GTLREF is equivalent to FSBxFSBVREF. GTLREF is generated from V
resistors.
V
V
V
specifications chapter in the document.
Leakage to VSS with land held at V
Leakage to V
Use 50 ohm ±15% for all Microstrip.
I
Regulator). Half of the total current goes through RTT on the chipset, and another half goes through the RTT on the CPU (the
End-Bus-Agency).
OL
IL
IH
IH
is defined as current when Output Low. The formula computes the total current drawn by the driver from VR (Voltage
is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
and V
is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
OH
may experience excursions above V
• (a) (b)
• (a) (b)
• (a) (c)
• (a) (c)
• (a) (c)
• (a) (b)
• (a) (b)
•
• (e)
•
TT
FSB Interface DC Characteristics
FSB Interface DC Characteristics
Signal
Group
with land held at 300 mV.
IH
®
) can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
Host AGTL+ Input Low
Voltage
Host AGTL+ Input High
Voltage
Host AGTL+ Output Low
Voltage
Host AGTL+ Output High
Voltage
Host AGTL+ Output Low
Current
Host AGTL+ Input Leakage
Current
Host AGTL+ Output
Leakage Current
Buffer on Resistance
Host Bus Reference
Voltage
Host Termination
Resistance Common Clock,
Async on Stripline
5000P chipset/Intel
Parameter
TT.
®
CC.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
5000V chipset and Intel
However, input signal drivers must comply with the signal quality
(0.98 x 0.67) x V
(0.1 × V
0.90 x V
GTLREF +
Min
n/a
n/a
45
0
7
TT
TT
)
TT
TT
®
on the baseboard by a voltage divider or 1%
5000X chipset External Design Specification
0.67 x
Nom
V
50
TT
(1.02 x 0.67) x V
R
tt_min
V
(0.1 × V
TT
GTLREF –
+/- 200
+/- 200
/ (0.50 x
Max
V
0.4
V
+ R
11
55
TT
TT
Electrical Characteristics
on_min
TT
)
TT
)
Unit
mA
uA
uA
V
V
V
V
Ω
V
Ω
Note
1, 2
1, 3
5, 6
5, 6
s
4
8
1
7