NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 302

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 5-3.
5.2.1.2
Figure 5-4.
302
Single DIMM Operation Mode
Mirrored Mode Memory Upgrades
When operating in mirrored mode both branches operate in lock step. In mirrored
mode Branch 1 contains a replicate copy of the data in Branch 0. For this reason the
minimum memory upgrade increment, for mirrored mode, is four DIMMs across all
branches. The DIMMs must cover the same slot position on both branches. DIMMs that
cover a slot position must be identical with respect to size, speed, and organization.
DIMMs within a slot position must match each other, but aren’t required to match
adjacent slot positions.
Figure 5-4
mode.
Minimum Mirrored Mode Memory Configuration
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
shows the minimum memory configuration required to operate in mirrored
CHANNEL 0
CHANNEL 0
BRANCH 0
BRANCH 0
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
CHANNEL 1
CHANNEL 1
Memory Controller
Memory Controller
SLOT 0
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 3
SLOT 2
SLOT 1
CHANNEL 2
CHANNEL 2
BRANCH 1
BRANCH 1
Functional Description
CHANNEL 3
CHANNEL 3