NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 376

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Table 5-25. I/O Port Registers in I/O Extender supported by Intel 5000P Chipset MCH
5.15.9.0.1Operation
376
When the Intel 5000P Chipset MCH comes out of reset, the I/O ports are inactive. After
a reset, the Intel 5000P Chipset MCH is not aware of how many IO Ports are connected
to it, what their addresses are, nor what PCI Express ports are hot-pluggable. The Intel
5000P Chipset MCH does not master any commands on the SMBus until a hot-plug
Capable bit is set.
For a PCI Express slot, an additional DIS_VPP bit is used to differentiate card or module
hot-plug support, DIS_VPP bit needs to be set to 0 to enable hot-plug support for PCI
Express card slot.
When BIOS sets a Hot-plug Capable bit (PEXSLOTCAP.HPC and PEXCTRL.DIS_VPP for
PCI Express; HPCTL.HPC for FB-DIMM HPU), the Intel 5000P Chipset MCH initializes the
associated VPP with Direction and Voltage Logic Level configuration as per
VPP registers for PCI Express which do not have the hot-plug capable bit set are invalid.
Additionally, if the DIS_VPP bit is set to 1, then the corresponding VPP register is invalid
for the PCI Express slot. This is intended for PCI Express module hot-plug which no VPP
support is required. The I/O Extender’s Polarity is left at its default value and never
written, but the direction and voltage logic levels are written using the addresses
defined in
When the Intel 5000P Chipset MCH is not doing a direction write, it performs input
register reads and output register writes to all valid VPPs. This sequence repeats
indefinitely until a new hot-plug capability bit is set. To minimize the completion time of
this sequence and minimize complexity, both ports are always read or written. For the
maximum number of 6 IO Ports, and assuming no clock stretching, this sequence can
take up to 51ms. If new hot-plug capability bits are not being set, this is the maximum
timing uncertainty in sampling or driving these signals.
Table 5-26
Register
0
1
2
3
4
5
6
7
Table
describes the Hot-Plug Signals used for hot-plug.
5-26.
Polarity Inversion Port 0
Polarity Inversion Port 1
Configuration Port 0
Configuration Port 1
Output Port 0
Output Port 1
Input Port 0
Input Port 1
Name
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Not written by Intel 5000P Chipset MCH
Intel 5000P Chipset MCH Usage
Continuously Writes Output Values
Continuously Reads Input Values
Direction set as per
Functional Description
Table 5-26
Table
5-26.