NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 332

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.6.2
5.6.3
5.6.4
332
Hardware IRQ IOxAPIC Interrupts
Dedicated pin interrupts may be edge or level triggered. They are routed to IRQ pins on
IOxAPIC device such as the Intel 6700PXH 64 bit PCI Hub, or Intel 631xESB/632xESB
I/O Controller Hub. The IOxAPIC device will convert the interrupt into either an XAPIC
or 8259 interrupt.
For level-triggered interrupts, the I/OxAPIC will generate an interrupt message when
any of the interrupt lines coming into it become asserted. The processor will handle the
interrupt and eventually write to the initiating device that the interrupt is complete. The
device will deassert the interrupt line to the I/OxAPIC. After the interrupt has been
serviced, the processor sends an EOI command to inform the I/OxAPIC that the
interrupt has been serviced. Since the EOI is not directed, the Intel 5000P Chipset will
broadcast the EOI transaction to all I/O(x)APIC’s. If the original I/O(x)APIC sees the
interrupt is still asserted, it knows there’s another interrupt (shared interrupts) and will
send another interrupt message.
For edge-triggered interrupts, the flow is the same except that there is no EOI message
indicating that the interrupt is complete. Since the interrupt is issued whenever an
edge is detected, EOIs are not necessary.
While not recommended, agents can share interrupts to better utilize each interrupt
(implying level-triggered interrupts). Due to ordering constraints, agents can not use
an interrupt controller that resides on a different PCI bus. Therefore either only agents
on the same PCI bus can share interrupts, or the driver MUST follow the PCI
requirement that interrupt routines must first read the PCI interrupt register
The Intel 5000P Chipset MCH supports the INTA (interrupt acknowledge) special bus
cycle for legacy 8259 support. These are routed to the compatibility ICH6 or ESB in the
system. The INTA will return data that provides the interrupt vector.
Message Signalled Interrupts
A second mechanism for devices to send interrupts is to issue the Message Signalled
Interrupt (MSI) introduced in the PCI Local Bus Specification, Revision 2.2. This
appears as a 1 DWORD write on the PCI/PCI-X/PCI Express bus.
With PCI devices, there are two types of MSIs. One type is where a PCI device issues
the inbound write to the interrupt range. The other type of MSI is where a PCI device
issues an inbound write to the upstream APIC controller (for example, in the Intel
6700PXH 64 bit PCI Hub) where the APIC controller converts it into an inbound write to
the interrupt range. The second type of MSI can be used in the event the OS doesn’t
support MSIs, but the BIOS does. In either way, the interrupt will appear as an inbound
write to the Intel 5000P Chipset over the PCI Express ports.
MSI is expected to be supported by the operating systems when the Intel 5000P
Chipset MCH is available. A Intel 5000P Chipset platform will also feature a backup
interrupt mechanism in the event that there is a short period of time when MSI is not
available. This is described in the next section.
Non-MSI Interrupts - “Fake MSI”
For interrupts coming through the Intel 6700PXH 64 bit PCI Hub, and Intel 631xESB/
632xESB I/O Controller Hub components, their APIC controller will convert interrupts
into inbound writes, so inbound interrupts will appear in the same format as an MSI.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Functional Description