NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 235

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.9.25
3.9.25.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
FB-DIMM IBIST Registers
FBD[3:2]IBPORTCTL: FB-DIMM IBIST Port Control Register
This register contains bits to control the operation of the IBIST DFT feature.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
31:26
7:4
3:2
1:0
Bit
Bit
25
RWST
RWST
RWST
Attr
Attr
RV
22
RV
280h, 180h
21
0
C1h, C0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
C1h, C0h
Intel 5000P Chipset
Default
Default
0h
01
00
0h
0
Reserved.
SBTXDRVCUR: South Bound Tx drive Current
00: 120% current
01: 100% current
10: 80% current
11: 60% current
SBTXDEEMP: South Bound Tx De-emphasis
With De-emphasis, the Tx differential p-p swing (eye height) is maintained at
nominal during data transitions, but drops down to the de-emphasized value
when there is no transition between the previous bit and current bit
00: No De-emphasis
01: -3.5dB
10: -6dB
11: -9.5 dB
Reserved
RXINVSWPMD: Rx Inversion Sweep Mode
0: Match Sweep according to the SB-to-NB_Mapping field in the TS1 training
sequence.
The default setting forces the RX inversion pointers to follow the unique
northbound inversion across the port width. It is based on a Modulo 5 of Intel
5000P Chipset MCHMAP bit setting. If e lanes Example;
If Intel 5000P Chipset MCHMAP = 0 then Lanes [4:0] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
If Intel 5000P Chipset MCHMAP = 1 then Lanes [9:5] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
For Intel 5000P Chipset MCH lane [13] does not exist but it does participate in
rotate-left-shift operations.
1: Enable full inversion sweep across the entire port.
When enabled the RX inversion pointers become a single entity.
Lanes [13:10] rotate left-shift completely across the width of the port. Even
though Lane[13] is a DFT lane it will be “shifted through” to make the logic
design easier.
0->1->2->3->4->5->6->7->8->9->10->11->12->13->0.
Description
Description
235