NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 15

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Introduction
1
Note:
1.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Introduction
The Intel
5000 sequence and supports a FSB frequency up to 1333 MTS. The Intel 5000P chipset
contains two main components: Memory Controller Hub (MCH) for the host bridge and
the I/O controller hub for the I/O subsystem. The Intel 5000P chipset uses the
Intel
The Intel
packaged in a 1432 pin FCBGA package with pins on 1.092 mm (37mil) centers. The
overall package dimensions are 42.5 mm by 42.5 mm.
The Intel 5000 Series chipset platform supports the Dual-Core Intel
series (1066 MHz with 2 MB L2 cache on 65nm process in a 771-land, FC-LGA4 (Flip
Chip Land Grid Array 4) package or the Dual-Core Intel
with 4 MB shared L2 cache) on 65 nm process in a 771-land, FC-LGA4 (Flip Chip Land
Grid Array 4) package. This package uses the matching LGA771 socket. The surface
mount, LGA771 socket supports Direct Socket Loading (DSL). The Dual-Core Intel Xeon
5000 sequence (1066/1333 MHz) returns a processor signature of 0F5xh where x is the
stepping number when the CPUID instruction is executed with EAX=1.
Unless otherwise specified, the term processor in this document refers to the Dual-Core
Intel Xeon 5000 sequence processors at both 1066MHz with 2 MB L2 cache and 1333
MHz with 4MB shared L2 cache on 65nm process in the 771-pin FC-LGA4 package.
Terminology
This section provides the definitions of some of the terms used in this document.
Agent
aka
Asserted
Atomic operation
Bank
Intel5000P MCH
Buffer
Cache Line
CDM
Cfg, Config
Terminology
®
631xESB/632xESB I/O Controller Hub.
®
®
5000P chipset is designed for systems based on the Dual-Core Intel
5000 Series chipsets are implemented in a 0.13 um silicon process and
A logical device connected to a bus or shared interconnect that can either initiate accesses
or be the target of accesses. Each thread executing within a processor is a unique agent.
also known as
Asserted Signal is set to a level that represents logical true. For signals that end with “#”
this means driving a low voltage. For other signals, it is a high voltage.
A series of operations, any one of which cannot be observed to complete unless all are
observed to complete.
DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank,
which is the only type the MCH supports. Each bank acts somewhat like a separate DRAM,
opening and closing pages independently, allowing different pages to be open in each.
Most commands to a DRAM target a specific bank, but some commands (i.e., Precharge
All) are targeted at all banks. Multiple banks allows higher performance by interleaving
the banks and reducing page miss cycles.
Intel 5000P North Bridge
1.
2.
The unit of memory that is copied to and individually tracked in a cache. Specifically, 64
bytes of data or instructions aligned on a 64-byte physical address boundary.
Central Data Manager. A custom array within the Intel® 5000P MCH that acts as a
temporary repository for system data in flight between the various ports: FSBs, FB-
DIMMs, ESI, and PCI Express.
Abbreviation for “Configuration”.
A random access memory structure.
The term I/O buffer is also used to describe a low level input receiver and output
driver combination.
Description
®
Xeon
®
5100 series (1333 MHz
®
Xeon
®
5000
®
Xeon
®
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