NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 366

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 5-34. DWORD Memory Read Protocol (SMBus Word Write / Word Read, PEC
Figure 5-35. WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled)
5.15.4
366
Disabled)
Slave SM Bus, SM Bus 0
System Management software in a Intel 5000P Chipset platform can initiate system
management accesses to the configuration registers via the Slave SM bus, SM Bus 0.
The mechanism for the Server Management (SM) software to access configuration
registers is through a SMBus Specification, Revision 2.0 compliant slave port. Some
Intel 5000P Chipset components contain this slave port and allow accesses to their
configuration registers. The product specific details are compatible with the Intel
631xESB/632xESB I/O Controller Hub SMBus configuration access mechanism. Most of
the Intel 5000P Chipset MCH registers can be accessed through the SMBus
configuration mechanism.
SMBus operations are made up of two major steps:
The following sections will describe the protocol for an SMBus master to access a Intel
5000P Chipset platform component’s internal configuration registers. Refer to the
SMBus Specification, Revision 2.0 for the bus protocol, timings, and waveforms.
1. Writing information to registers within each component
2. Reading configuration registers from each component.
S
S
S
Sr
S
Sr
S
S
Sr
S
S
S
S
S
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
W A
W A
W A
W A
R A
R A
W A
R A
W A
W A
W A
W A
W A
W A
Cmd = 10100001
Cmd = 10100001
Cmd = 00100001
Cmd = 01100001
Cmd = 01100000
Data[23:16]
Status
Data[7:0]
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Cmd = 00001000
Cmd = 10001000
Cmd = 00001000
Cmd = 00001000
Cmd = 00001000
Cmd = 01001000
A
A
A
A
A
A
A
N
P
Add Offset[15:8]
Data[31:24]
Dest Mem
Data[15:8]
A
A
A
A
A
A
Register Num[15:8]
Register Num[7:0]
Device/Function
Bus Number
N P
N P
Data[W:X]
A
A
Data[Y:Z]
Add Offset[23:16]
Add Offset[7:0]
A P
Functional Description
A P
CLOCK STRETCH
A P
A P
A P
A
CLOCK STRETCH
P
A P
A P