NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 367

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Table 5-21. SMBus Address for Product Name Platform
5.15.4.1
Table 5-22. SMBus Command Encoding
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Each component on the Intel 5000P Chipset platform must have a unique address. Intel
5000P Chipset platform component addresses are defined in the following table.
Supported SMBus Commands
Product Name components SMBus Rev. 2.0 slave ports support the following six SMBus
commands:
Sequencing these commands will initiate internal accesses to the component’s
configuration registers.
Each configuration read or write first consists of an SMBus write sequence which
initializes the Bus Number, Device Number, and so forth. The term sequence is used
since these variables may be written with a single block write or multiple word or byte
writes. Once these parameters are initialized, the SMBus master can initiate a read
sequence (which perform a configuration read) or a write sequence (which performs a
configuration write).
Each SMBus transaction has an 8-bit command driven by the master. The format for
this command is illustrated in
The Begin bit indicates the first transaction of a read or write sequence.
The End bit indicates the last transaction of a read or write sequence.
The Pecan bit enables the 8-bit Packet Error Code (PEC) generation and checking logic.
The Internal Command field specifies the internal command to be issued by the SMBus
slave logic. Note that the Internal Command must remain consistent during a sequence
that accesses a configuration register. Operation cannot be guaranteed if it is not
consistent when the command setup sequence is done.
The SMBus Command field specifies the SMBus command to be issued on the bus. This
field is used as an indication of the length of transfer so the slave knows when to
expect the Packet Error Code packet.
Reserved bits should be written to zero to preserve future compatibility.
Begin
• Block Write
• Block Read
7
Intel 5000P Chipset MCH
End
Component
6
Rsvd
5
PEC_en
Table 5-22
4
• Word Write
• Word Read
SMBus Address
Internal Command:
00 - Read DWord
01 - Write Byte
10 - Write Word
11 - Write DWord
1100_000
(7:1)
below.
3:2
• Byte Write
• Byte Read
SMBus Command:
00 - Byte
01 - Word
10 - Block
11 - Rsvd
1:0
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