NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 3

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Contents
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Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Introduction............................................................................................................... 15
1.1
1.2
1.3
Signal Description....................................................................................................... 25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Register Description.................................................................................................... 45
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Terminology ..................................................................................................... 15
Related Documents and Materials ........................................................................ 21
1.2.1
Intel 5000P Chipset Overview ............................................................................. 21
Processor Front Side Bus Signals ......................................................................... 27
2.1.1
2.1.2
Fully Buffered DIMM Memory Channels................................................................. 31
2.2.1
2.2.2
PCI Express* Signal List ..................................................................................... 32
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
System Management Bus Interfaces .................................................................... 35
XD Port Signal List............................................................................................. 35
JTAG Bus Signal List .......................................................................................... 35
Clocks, Reset and Miscellaneous .......................................................................... 36
Power and Ground Signals .................................................................................. 36
MCH Sequencing Requirements ........................................................................... 36
Reset Requirements........................................................................................... 38
2.10.1 Timing Diagrams .................................................................................... 38
2.10.2 Reset Timing Requirements ..................................................................... 40
2.10.3 Miscellaneous Requirements and Limitations .............................................. 41
Intel 5000P Chipset Platform Signal Routing Topology Diagrams .............................. 42
2.11.1 Intel 5000P Customer Reference Platform (SRP) Reset Topology................... 43
Signals Used as Straps....................................................................................... 43
2.12.1 Functional Straps ................................................................................... 43
Register Terminology ......................................................................................... 45
Platform Configuration Structure ......................................................................... 46
Routing Configuration Accesses ........................................................................... 48
3.3.1
3.3.2
3.3.3
Device Mapping................................................................................................. 50
3.4.1
3.4.2
I/O Mapped Registers ........................................................................................ 53
3.5.1
3.5.2
MCH Fixed Memory Mapped Registers .................................................................. 54
Detailed Configuration Space Maps ...................................................................... 55
BIOS Self-test Utility............................................................................... 21
Processor Front Side Bus 0 ...................................................................... 27
Processor Front Side Bus 1 ...................................................................... 29
FB-DIMM Branch 0 ................................................................................. 31
FB-DIMM Branch 1 ................................................................................. 32
PCI Express* Common Signals ................................................................. 32
PCI Express Port 0, Enterprise South Bridge Interface (ESI) ......................... 33
PCI Express Port 2.................................................................................. 33
PCI Express Port 3.................................................................................. 33
PCI Express Port 4.................................................................................. 34
PCI Express Port 5.................................................................................. 34
PCI Express Port 6.................................................................................. 34
PCI Express Port 7.................................................................................. 34
Standard PCI Bus Configuration Mechanism ............................................... 49
PCI Bus 0 Configuration Mechanism .......................................................... 49
Primary PCI and Downstream Configuration Mechanism............................... 49
Device Identification for Intel 5000P Chipset, Intel 5000Z Chipset,
and Intel 5000V Chipset Components........................................................ 51
Special Device and Function Routing ......................................................... 51
CFGADR: Configuration Address Register................................................... 53
CFGDAT: Configuration Data Register ....................................................... 53
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