NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 342

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.11.4
5.11.5
5.11.6
5.11.6.1
5.11.6.2
5.12
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Legacy Interrupt Messages
The ESI and PCI Express interfaces support two methods for handling interrupts: MSI
and legacy interrupt messages. The interrupt messages are a mechanism for taking
traditionally out-of -band interrupt signals and using in-band messages to
communicate. Each PCI Express interface accepts up to four interrupts (A through D)
and each interrupt has an assert/deassert message to emulate level-triggered
behavior. The MCH effectively wire-ORs all the INTA messages together (INTBs are
wire-ORed together, and so forth).
When the MCH accepts these PCI Express interrupt messages, it aggregates and passes
the corresponding “assert_intx” messages to the Intel 631xESB/632xESB I/O
Controller Hub’s I/OAPIC with from the PCI Express ports (wired-OR output transitions
from 0− >1) mechanism. When the corresponding deassert_intx message is received at
all the PCI Express ports (wired-OR output transitions from 1− >0), the “deassert_intx”
message is sent to ESI port.
End-of-Interrupt (EOI) Support
The EOI is a specially encoded processor bus transaction with the interrupt vector
attached. Since the EOI is not directed, the MCH will broadcast the EOI transaction to
all I/O(x)APICs. The MCH.PEXCTRL.DIS_APIC_EOI bit per PCI Express port can be used
to determine whether an EOI needs to be sent to a specific port.
Error Handling
Table 5-31
Advanced error reporting mechanism.
Inbound Errors
In general, if an inbound read transaction results in a Master Abort (unsupported
request), the compatibility interface cluster returns a Master Abort completion with
data as all ones. Likewise, for a Target Abort condition, the ESI cluster returns a Target
Abort completion with data as all ones. If a read request results in a Master or Target
Abort, the MCH returns the requested number of data phases with all ones data.
Master aborted inbound writes are dropped by the MCH, the error is logged, and the
data is dropped.
If the MCH receives an inbound unsupported Special Cycle message it is ignored and
the error condition is logged. If the completion required bit is set, an Unsupported
Special Cycle completion is returned.
Outbound Errors
It is possible that the compatibility interface cluster will receive an error response for
an outbound request. This can include a Master or Target Abort for requests that
required completions. The MCH might also receive an “Unsupported Special Cycle”
completion.
PCI Express Ports
The Intel 5000P Chipset MCH contains two classes of PCI Express derived ports. These
are:
describes the errors detected on ESI through the standard PCI Express and
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Functional Description