NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 312

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.2.10.4
312
When the branch operates in single-channel/single-DIMM mode, the Intel 5000P
Chipset MCH employs x8 SDDC as in the dual channel case. However, in this case, the
ECC RAS feature set is limited for the single DIMM memory subsystem. In the single
DIMM mode (for example, nine x8 devices), the SDDC cannot correct single wire fault
(stuck-at) errors or permanent full device errors. This is because the error correction
capability in the SDDC is limited to adjacent symbol errors on a 16-bit boundary and in
the single DIMM mode with a Burst Length of 8, there are 4 transfers of 8B to form a
32Bcode word. Hence a single wire failure in the same device is replicated across all 4
symbols hampering the error correction. The SDDC can detect most x4/x8 DRAM
failures but it can only correct adjacent symbol errors that occur within a 16-bit
boundary of each code word.
Inbound ECC Code Layout for Dual-Channel Branches
The code is systematic: that is, the data is separated from the check-bits rather than all
being encoded together. It consists of 32 eight-bit data symbols (DS31-DS0) and four
eight-bit Check-bit Symbols (CS3-CS0). The code corrects any two adjacent symbols in
error. The symbols are arranged so that the data from every x8 DRAM is mapped to two
adjacent symbols, so any failure of the DRAM can be corrected.
Figure 5-8
symbols are mapped on the FB-DIMM branch and to DRAM bits by the DIMM for a
transfer in which the critical 16 B is in the lower half of the code-word (A[4]=0). If the
upper portion of the code-word were transferred first, bits[7:4] of each symbol would
be transferred first on the DRAM interface and in the first six transfers on the FB-DIMM
channel. The layout for branch 1 is the same.
The bits of Data Symbol 0 (DS0) are traced from DRAM to FB-DIMM Northbound. The
same mapping of symbols to data and code bits applies to Southbound data. The lower
nibble (DS0A) consists of DS0[3:0] the upper nibble (DS0B) consists of DS0[7:4]. On
the DRAM interface, DS0 is expanded to show that it occupies 4 DRAM lines for two
transfers. DS0[3:0] appears in the first transfer. DS0[7:4] appear in the second
transfer. DS0 and DS1 are the adjacent symbols that protect the eight lines from the
first DRAM on DIMM0. The same DS0 is shown expanded on the Northbound FB-DIMM
interface where it occupies the FD0NB[P:N][0] signal. DS0 and DS1 cover all transfers
on FD0NB[P:N][0] (even though FD0NB[P:N][0] does not cover all of DS1).
• Detection of all permutations of 2 x4 DRAM failures.
illustrates the ECC code layout for branch 0. The figure shows how the
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Functional Description