NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 291

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

System Address Map
Note:
Table 4-9.
a. SMM memory access control, see
b. Software must not cache this region.
c. One and only one BCTRL can set the VGAEN; otherwise, send to ESI.
d. Notice this range is mapped into legacy SMM range (A_0000h to B_FFFFh).
4.4.3
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Notes:
SMM region
Legacy
VGA/SMM
Extended
SMRAM
(TSEG)
High SMM
b
A_0000h
to
B_FFFFh
ESMMTOP -TSEG_SZ
to
ESMMTOP
FEDA_0000h
to
FEDB_FFFFh
The Intel 5000P Chipset prevents illegal processor access to SMM memory. This is
accomplished by routing memory requests from processors as a function of transaction
request address, code or data access, the SMMEM# signal accompanying request and
the settings of the Intel 5000P Chipset MCH.SMRAMC, Intel 5000P Chipset
MCH.EXSMRC, and Intel 5000P Chipset MCH.BCTRL registers.
5000P Chipset MCH’s routing for each case. Illegal accesses are either routed to the ESI
bus where they are Master Aborted or are blocked with error flagging. SMMEM# only
affects Intel 5000P Chipset behavior if it falls in an enabled SMM space. Note that the
D_CLS only applies to the legacy (A_0000-B_FFFF) SMM region. The bold values
indicate the reason SMM access was granted or denied.
If a spurious inbound access targets the enabled SMM range (viz., legacy, High SMM
Memory and Extended SMRAM (T-segment)), then it will be Master-aborted. The
EXSMRAMC.E_SMERR register field (Invalid SMRAM) is set for accesses to the High
SMM Memory and Extended SMRAM (T-segment)). Refer to
Decoding Processor Requests to SMM and VGA Spaces
Inbound Transactions
In general, inbound I/O transactions are decoded and dispositioned similarly to
processor transactions. The key differences are in SMM space, memory mapped
configuration space, and interrupts. Inbound transaction targeting at itself will be
master aborted.
Note that inbound accesses to the SMM region must be handled in such a way that FSB
snooping and associated potential implicit writebacks are avoided. This is necessary to
prevent compromising SMM data by returning real content to the I/O subsystem. Note
also that DMA engine is treated as an I/O device, thus accesses initiated by the DMA
engine are considered as inbound accesses.
Transaction
Address
Range
Table
A_0000h
to
B_FFFFh
ESMMTOP -TSEG_SZ
to
ESMMTOP
A_0000h
to
B_FFFFh
4-8.
SMM Memory
Address
Range
x
yes
no
yes
x
x
yes
no
no
x
x
yes
no
no
Control
Access
SMM
a
0
1
1
1
0
1
1
1
1
0
1
1
1
1
x
1
x
0
x
x
x
x
x
x
0
1
1
1
x
x
x
x
x
0
1
1
1
x
x
x
x
x
Table
x
x
x
x
x
x
x
1
0
x
x
x
1
0
Table 4-9
to the VGA-enabled port (in
BCTRL);
otherwise, ESI
to SMM memory
to identical system memory
by definition
to SMM memory
block access: master abort
set EXSMRAMC.E_SMERR
to ESI (where access will be
master aborted)
to SMM memory
block access: master abort
set EXSMRAMC.E_SMERR
4-10.
defines Intel
Routing
c
d
291