FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 631
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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Testability
21.1
.
Intel
®
Table 196. Test Mode Selection
Figure 27. Test Mode Entry (XOR Chain Example)
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: RTCRST# can be driven low any time after PCIRST# is inactive.
Test Mode Description
The ICH5 supports two types of test modes, a tri-state test mode and a XOR Chain test mode.
Driving RTCRST# low for a specific number of PCI clocks while PWROK is high will activate a
particular test mode as described in
Figure 27
edge of the RTCRST# after being asserted for a specific number of PCI clocks while PWROK is
active. To change test modes, the same sequence should be followed again. To restore the ICH5 to
normal operation, execute the sequence with RTCRST# being asserted so that no test mode is
selected as specified in
Number of PCI Clocks RTCRST#
driven low after PWROK active
Other Signal
RSMRST#
RTCRST#
PWROK
Outputs
illustrates the entry into a test mode. A particular test mode is entered upon the rising
43
9
>53
<4
–
52
53
–
4
5
6
7
8
42
51
Table
196.
Table
All Output Signals Tri-Stated
Reserved. DO NOT ATTEMPT
N Number of PCI Clocks
196.
No Test Mode Selected
No Test Mode Selected
No Test Mode Selected
XOR Chain 4 Bandgap
XOR Chain 1
XOR Chain 2
XOR Chain 3
XOR Chain 4
XOR Chain 6
Test Mode
All “Z”
XOR Chain Output Enabled
Test Mode Entered
Testability
21
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