FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 222
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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Functional Description
5.20.7.4
5.20.8
222
ACPI System States
The EHC behavior as it relates to other power management states in the system is summarized in
the following list:
Interaction with UHCI Host Controllers
The Enhanced Host controller shares the eight USB ports with four UHCI Host controllers in the
ICH5. The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the UHC
at D29:F2 shares ports 4 and 5; and the UHC at D29:F3 shares ports 6 and 7 with the EHC. There
is very little interaction between the Enhanced and the UHCI controllers other than the muxing
control which is provided as part of the
conceptual level.
— The System is always in the S0 state when the EHC is in the D0 state. However, when the
— When in D0, the Pause feature (See
— The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power turns off).
— All core well logic is reset in the S3/S4/S5 states (core power turns off).
EHC is in the D3 state, the system may be in any power management state (including S0).
power states to be entered.
EHC.Figure 24
Section
Intel
®
5.20.7.1) enables dynamic processor low-
82801EB ICH5 / 82801ER ICH5R Datasheet
shows the USB Port Connections at a
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