FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 456
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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SATA Controller Registers (D31:F2)
11.2
456
Table 158. Bus Master IDE I/O Register Address Map
Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers
can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an
indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be
attempted). The description of the I/O registers is shown in
0C–0F
Offset
04–07
0A
0B
00
01
02
03
08
09
Mnemonic
BMICP
BMISP
BMIDP
BMICS
BMISS
BMIDS
—
—
—
—
Command Register Primary
Reserved
Bus Master IDE Status Register Primary
Reserved
Bus Master IDE Descriptor Table Pointer Primary
Command Register Secondary
Reserved
Bus Master IDE Status Register Secondary
Reserved
Bus Master IDE Descriptor Table Pointer Secondary
Register Name
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Table
158.
Default
01h
00h
01h
00h
—
—
xx
—
—
xx
R/W, R/WC,
R/W, R/WC,
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
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