FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 488
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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EHCI Controller Registers (D29:F7)
13.1.19
13.1.20
488
PWR_CNTL_STS—Power Management Control/Status
Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
14:13
12:9
Bit
7:2
1:0
Bit
7:0
15
8
PME Status — R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if enabled).
1 = This bit is set when the Intel
NOTE: This bit must be explicitly cleared by the operating system each time the operating system
Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data register.
Data Select — RO. Hardwired to 0000b indicating it does not support the associated Data register.
PME Enable — R/W.
0 = Disable
1 = Enable. Enables ICH5 EHC to generate an internal PME signal when PME_Status is 1.
NOTE: This bit must be explicitly cleared by the operating system each time it is initially loaded.
Reserved
Power State — R/W. This 2-bit field is used both to determine the current power state of EHC
function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3 hot state
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs. When in the D3 hot state, the
ICH5 must not accept accesses to the EHC memory range; but the configuration space must still be
accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically,
the PIRQH is not asserted by the ICH5 when not in the D0 state.
When software changes this value from the D3hot state to the D0 state, an internal warm (soft) reset
is generated, and software must re-initialize the function.
Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a Debug Port
Capability structure.
the state of the PME_En bit.
is loaded.
54
0000h
58h
0Ah
–
55h
®
ICH5 EHC would normally assert the PME# signal independent of
Description
Intel
Description
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, R/WC, RO
16 bits
RO
8 bits
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