FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 334
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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LPC Interface Bridge Registers (D31:F0)
9.1.25
334
RTC_CONF—Real Time Clock Configuration Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
Bit
7:5
1:0
4
3
2
Reserved
Upper 128-byte Lock (U128LOCK) — R/WO.
0 = Access to these bytes in the upper CMOS RAM range have not been locked.
1 = Locks reads and writes to bytes 38h–3Fh in the upper 128-byte bank of the RTC CMOS RAM.
Lower 128-byte Lock (L128LOCK) — R/WO.
0 = Access to these bytes in the lower CMOS RAM range have not been locked.
1 = Locks reads and writes to bytes 38h–3Fh in the lower 128-byte bank of the RTC CMOS RAM.
Upper 128-byte Enable (U128E) — R/W.
0 = Disable
1 = Enables access to the upper 128-byte bank of RTC CMOS RAM.
Reserved
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
D8h
00h
Yes
Intel
Description
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, R/WO
8 bit
Core
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