FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 419
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FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
Lead Free Status / RoHS Status
Not Compliant
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10.1.5
10.1.6
10.1.7
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RID—Revision Identification Register
(IDE—D31:F1)
Offset Address:
Default Value:
PI—Programming Interface Register
(IDE—D31:F1)
Address Offset:
Default Value:
SCC—Sub Class Code Register
(IDE—D31:F1)
Address Offset:
Default Value:
Bit
7:0
Bit
6:4
Bit
7:0
7
3
2
1
0
Revision ID — RO. This 8-bit value indicates the revision number for IDE controller.
NOTE: Refer to the latest Intel
This read-only bit is a 1 to indicate that the Intel
Reserved. Hardwired to 000b.
SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary controller supports
both legacy and native modes.
SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary IDE channel
is operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller supports
both legacy and native modes.
POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary IDE channel is
operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
Sub Class Code (SCC) — RO.
01h = IDE device, in the context of a mass storage device.
Identification register.
08h
See bit description
09h
8Ah
0Ah
01h
®
ICH5 / ICH5R Specification Update for the value of the Revision
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
ICH5 supports bus master operation.
IDE Controller Registers (D31:F1)
R/W, RO
8 bits
RO
8 bits
RO
8 bits
419
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