FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 271
FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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Intel
®
Table 131. Fixed I/O Ranges Decoded by Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
NOTES:
1. Only if IDE Standard I/O space is enabled for Primary Channel and the IDE Controller is in legacy mode.
2. Only if IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller is in legacy mode.
3. If POS_DEC_EN bit is enabled, reads from F0h will not be decoded by the ICH5. If POS_DEC_EN is not
I/O Address
4D0h–4D1h
1F0h–1F7h
170h–177h
Otherwise, the target is PCI.
Otherwise, the target is PCI.
enabled, reads from F0h will forward to LPC.
ACh–ADh
BCh–BDh
D2h–DDh
DEh–DFh
8Ch–8Eh
A0h–A1h
A4h–A5h
A8h–A9h
B0h–B1h
B2h–B3h
B4h–B5h
B8h–B9h
C0h–D1h
89h–8Bh
93h–9Fh
81h–83h
84h–86h
90h–91h
CF9h
08Fh
3F6h
376h
F0h
87h
88h
92h
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Reset Generator
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Power Management
Interrupt Controller
Interrupt Controller
Interrupt Controller
DMA Controller
RESERVED
DMA Controller
See Note 3
IDE Controller
IDE Controller
IDE Controller
IDE Controller
Interrupt Controller
Reset Generator
Read Target
2
1
2
1
®
ICH5 (Sheet 2 of 2)
DMA Controller
DMA Controller and LPC or PCI
DMA Controller
DMA Controller and LPC or PCI
DMA Controller
DMA Controller and LPC or PCI
DMA Controller
DMA Controller
Reset Generator
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Power Management
Interrupt Controller
Interrupt Controller
Interrupt Controller
DMA Controller
DMA Controller
DMA Controller
FERR#/IGNNE# / Interrupt
Controller
IDE Controller
IDE Controller
IDE Controller
IDE Controller
Interrupt Controller
Reset Generator
Write Target
2
1
2
1
Register and Memory Mapping
DMA
DMA
DMA
DMA
Processor I/F
DMA
Power Management
DMA
DMA
Processor I/F
Forwarded to IDE
Forwarded to IDE
Forwarded to IDE
Forwarded IDE
Processor I/F
DMA
DMA
DMA
DMA
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
DMA
Interrupt
Internal Unit
271
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