RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 43

• Manufacturer Part Number: RD38F2240WWYTQ0SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWYTQ0SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
Table 19: PSRAM Refresh Control Register Map
Table 20: PSRAM Refresh Control Register Description
9.3.2.1
Warning:
9.3.2.2
November 2007
Order Number: 311760-10
DQ[15:0]
A[MAX:0
]
RCR Bit
RCR Bit
22:20
19:18
17:8
6:5
2:0
7
4
3
Reserved
Register Select
Reserved
Page Mode
Reserved
Deep Power Down (DPD)
Reserved
Partial Array Self Refresh
Reserved
A22 - A20
22 - 20
PSRAM Page Mode RCR Bit
In asynchronous (SRAM) mode, the user has the option to enable page mode. Page
mode applies only to asynchronous read operations and has no impact on
asynchronous write operations. In synchronous and NOR-Flash modes, the page mode
setting has no impact on PSRAM operation. The maximum page length is 16 words, so
A[3:0] is regarded as the page address.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7
must be set to Zero.
PSRAM Deep-Power Down RCR Bit
To put the device in deep power down mode the DPD control bit must be set low
(RCR4 =0.) All internal voltage generators inside the PSRAM are switched off and the
internal self-refresh is stopped. This means that all stored memory information will be
lost by entering DPD. Only the register values of BCR, and RCR remain valid during
DPD.
A19
19
Register
Select
NAME
A18
18
DQ16-DQ8
Reserved
A17 - A8
17 - 8
Mode
Page
DQ7
A7
7
Reserved bits should be set to ‘0’ during set control register
commands
00 = Select RCR
Reserved bits should be set to ‘0’ during set control register
commands
0 = Page Mode disabled (Default)
1 = Page Mode enabled
Reserved bits should be set to ‘0’ during set control register
commands
0 = DPD enabled
1 = DPD disabled (Default)
Reserved bits should be set to ‘0’ during set control register
commands
000 = Full array refreshed (Default)
001 = Bottom 1/2 of array refreshed
010 = Bottom 1/4 of array refreshed
011 = Bottom 1/8 of array refreshed
100 = None of array refreshed
101 = Top1/2 of array refreshed
110 = Top1/4 of array refreshed
111 = Top1/8 of array refreshed
DQ6
Reserved
A6
6
DQ5
A5
5
Down (DPD)
Deep Power
DQ4
A4
4
Description
Reserved
DQ3
A3
3
DQ2
A2
2
PASR
DQ1
A1
1
Datasheet
DQ0
A0
0
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