RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 20
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RD38F2240WWYTQ0SB93
Manufacturer Part Number
RD38F2240WWYTQ0SB93
Description
Manufacturer
Micron Technology Inc
Datasheet
1.RD38F2240WWYTQ0SB93.pdf
(54 pages)
Specifications of RD38F2240WWYTQ0SB93
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Table 11: PSRAM AC Characteristics—Asynchronous Read
Notes:
1.
2.
3.
4.
5.
Datasheet
20
Symbol
t
t
ASKEWP
t
t
ASKEW
t
t
t
t
t
AADV
t
t
t
t
t
t
CRES
t
t
t
t
t
t
t
t
t
AVH
AVS
CVS
t
BHZ
OLZ
OHZ
VPH
CPH
PAA
CSL
BLZ
OH
CO
RC
AA
PC
BA
OE
HZ
LZ
VP
Timing parameters are at the default output drive strength (half drive strength).
t
Applies to ADV# controlled Asynchronous Read operations.
Applies when control signals (ADV#, CS#, UB#/LB#) are active.
When operating the PSRAM as an ADMux I/O interface, Page-Mode operation is not available.
CSL
max limit applies during asynchronous reads when page mode is enabled.
Read Cycle Time
Address Access Time
ADV# Access Time
Page Address Cycle Time
Page Address Access Time
Address Hold from ADV# High
Address Setup to ADV# High
CE# Low to ADV# High
Output Hold from Address Change
CE# Access Time
UB#, LB# Access Time
OE# to Valid Output Data
CE# Pulse Width Low Time
CE# Low to Output Low-Z
CE# High to Output High-Z
UB#, LB# Low to Output Low-Z
UB#, LB# High to Output High-Z
OE# Low to Output Low-Z
OE# High to Output HIgh-Z
ADV# Pulse Width Low
ADV# Pulse Width High
UB#, LB# and CE# Pulse Width High
CRE Setup to CE# Low
Address Skew (Non-Page Access)
Page Mode Access Address Skew [A3:A0]
Parameter
128-Mbit W18 Family with Synchronous PSRAM
Min
70
20
10
10
10
10
10
—
—
—
—
—
—
—
—
—
5
5
6
0
6
0
3
0
0
Max
70
70
70
70
20
20
10
—
—
—
—
—
—
—
—
—
—
—
—
—
8
8
8
4
2
Order Number: 311760-10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
November 2007
Notes
1,3
1,3
1,3
1,2
1,3
1,3
1,4
1,5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1