RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 32

• Manufacturer Part Number: RD38F2240WWYTQ0SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWYTQ0SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Warning:
8.1.2
Warning:
8.1.3
Warning:
8.1.4
Datasheet
32
Valid data is available on the data bus after the specified access time has elapsed.
WAIT output is driven, but should be ignored for asynchronous-mode read operations.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Asynchronous Page-Mode Read
Page mode allows toggling of the four lower address bits (A3 to A0) to perform
subsequent random read accesses (max. 16-words by A3-A0) at much faster speed
than the 1
PSRAM. Once page mode is enabled by appropriately setting the BCR, tCSL restrictions
will apply to asynchronous Read accesses. Therefore CE# will have to be pulled high at
least every tCSL period during asynchronous Read operations. ADV# has to be held low
for the entire page operation.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7
must be set to Zero.
PSRAM Synchronous Burst-Mode Reads
In the Full Synchronous mode and NOR-Flash mode, PSRAM read operations are
synchronous. A BURST INIT READ command is used to initiate a synchronous read
operation and latch the burst start address. To initiate a synchronous read operation:
To continue the synchronous read operation:
The first data word is output after the number of clock cycles defined by the
programmed latency mode and latency count in the BCR. Subsequent data words are
output at successive clock cycles after the first data word.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Asynchronous Fetch Control Register Read
In the Asynchronous (SRAM-type) mode the contents of the BCR and RCR can be read
asynchronously. To initiate an asynchronous Fetch Control Register (FCR):
• CE#, ADV#, and both UB# and LB# must be asserted;
• WE# and CRE must be deasserted; and
• Burst start address is latched on the rising edge of the clock;
• CE#, OE#, and both UB# and LB# must be asserted; and
• ADV# must be deasserted;
• WAIT output will be driven and should be monitored in Variable Latency mode.
• WAIT may be ignored in fixed latency mode.
• Both UB# and LB# must be held static low for the entire read access. The size of
• CE#, OE#, CRE, and both UB# and LB# must be asserted;
• WE# must be deasserted;
• ADV# can be toggled to latch the address or held low for the entire read operation;
the burst is also specified in the BCR.
st
read access. Only page mode Read operations are supported by the
128-Mbit W18 Family with Synchronous PSRAM
Order Number: 311760-10
November 2007