RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 34

• Manufacturer Part Number: RD38F2240WWYTQ0SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWYTQ0SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Warning:
8.2.3
Warning:
8.2.4
Warning:
8.3
Datasheet
34
synchronous write is always at fixed latency regardless of the Latency Mode setting,
WAIT may be ignored. UB# or LB# may be deasserted to mask the associated data
byte.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Asynchronous Set Control Register Write
In the Asynchronous (SRAM-type) mode and NOR-Flash mode the contents of the BCR
and RCR can be set asynchronously. To initiate an asynchronous Set Control Register:
The DQ signals are ignored by the PSRAM. Address bits A19 and A18 specify the target
register (RCR = 00b, BCR = 10b.) The values of the remaining address bits are loaded
into the selected register. The Set Control Register command should only be issued
when the PSRAM is in the idle state (deselected).
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Synchronous Set Control Register Write
In the full Synchronous mode the contents of the BCR and RCR can be set
synchronously. To initiate a synchronous Set Control Register:
The DQ signals are ignored by the PSRAM and therefore the WAIT signal should be
ignored. Address bits A19 and A18 specify the target register (RCR = 00b, BCR = 10b.)
The values of the remaining address bits are loaded into the selected register. The Set
Control Register command should only be issued when the PSRAM is in the idle state
(deselected).
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM No Operation Command
The No Operation (NOP) command is used to perform a no operation to a selected
PSRAM (CE# = Low) Operations in progress are not affected. A NOP may be issued in
Asynchronous, Synchronous, or NOR-Flash mode. To initiate a NOP:
• CE#, WE#, and CRE must be asserted;
• OE# must be deasserted;
• ADV# can be toggled to latch the address or held low for the entire read operation;
• CLK must be held in a static low state.
• CE#, WE#, ADV#, and CRE must be asserted; and
• OE# must be deasserted;
• Address is latched on the rising edge of the clock
• CE#, must be asserted;
• WE#, ADV#, OE#, and CRE must be deasserted; and
• CLK must be held in a static low state while in Asynchronous mode. CLK may toggle
during a NOP in Synchronous mode.
128-Mbit W18 Family with Synchronous PSRAM
Order Number: 311760-10
November 2007