RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 39

• Manufacturer Part Number: RD38F2240WWYTQ0SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWYTQ0SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
Table 15: Bus Control Register Description
9.3.1.1
November 2007
Order Number: 311760-10
BCR Bit
13:11
7:6
5:4
2:0
10
9
8
3
Latency Counter
WAIT Polarity
Reserved
WAIT Configuration
Reserved
Drive Strength
Burst Wrap
Burst Length
PSRAM BCR Operating Mode
The PSRAM supports three different interface access protocols:
Operating the PSRAM in synchronous mode maximizes bandwidth. The NOR-Flash type
mode is the recommended mode for legacy systems which are not able to run the
synchronous write protocol. The Operating Mode bit BCR15 defines whether the device
is operating in synchronous (fully or partially) mode or asynchronous mode.
When BCR15 is set low, the mode of write operation, NOR-flash or Full synchronous, is
adaptively detected by detecting a rising clock edge during ADV# valid. If a rising clock
edge occurs within ADV# valid, Full synchronous write is detected. If there is no rising
clock edge then NOR-Flash write is detected and CE# must go high when transitioning
from asynchronous to synchronous operation or when transitioning from synchronous
to asynchronous operation..
When BCR15 is set high, the SRAM-type mode of operation is selected.
• SRAM-type protocol with asynchronous read and write accesses
• NOR-Flash-type protocol with synchronous read and asynchronous write accesses
• FULL SYNCHRONOUS mode with synchronous read and synchronous write accesses
NAME
000 = Code 0 - Reserved
001 = Code 1 - Reserved
010 = Code 2
011 = Code 3 (Default)
100 = Code 4
101 = Code 5
110 = Code 6
111 = Code 7 - Reserved
0 = Active Low
1 = Active High (Default)
Reserved bits should be set to ‘0’ during set control register commands
0 = WAIT asserted during delay
1 = WAIT asserted one data cycle before delay (Default)
Reserved bits should be set to ‘0’ during set control register commands
00 = Full
01 = 1/2 (Default)
10 = 1/4
11 = Reserved
0 = Burst wraps within the burst length
1 = Burst does not wrap (Default)
000 = Reserved
001 = 4 words
010 = 8 words
011 = 16 words
100 = 32 words
101 = Reserved
110 = Reserved
111 = Continuous Burst (Default)
Description
Datasheet
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