RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 38

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RD38F2240WWYTQ0SB93

Manufacturer Part Number
RD38F2240WWYTQ0SB93
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of RD38F2240WWYTQ0SB93

Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
9.3
9.3.1
Table 14: PSRAM Bus Control Register Map
Table 15: Bus Control Register Description
Datasheet
38
DQ
[15:0]
A
[MAX:0
]
BCR Bit
BCR Bit
22:20
19:18
17:16
15
14
A22
-
A20
22-
20
Reserved
Register Select
Reserved
Operating Mode
Initial Latency
A1
9
19
PSRAM Control Registers
The PSRAM includes two control registers that define the PSRAM device operation. The
Bus Control Register (BCR) defines how the PSRAM interacts with the system memory
busy, and the Refresh Control Register (RCR) defines low-power refresh modes. Both
these registers are loaded with default values on power-up and can be updated at any
time using hardware or software access method.
PSRAM Bus Control Register
The Bus Control Register (BCR) specifies the interface configurations. The Bus Control
Register is programmed via the Set Control Register command (with CRE = 1 and
A[19:18] = 10b) and retains the stored information until it is reprogrammed or the
device loses power.
Reserved bit fields of the BCR should be ignored during a Fetch Control Register
command as they may have undefined values even when set to 0b with a Set Control
Register command. The BCR contents can only be set or changed when the PSRAM is in
idle state.
A1
8
18
NAME
A17
-
A16
17-
16
DQ1
5
A15
15
DQ1
4
A14
14
Reserved bits should be set to ‘0’ during set control register commands
10 = Select BCR
Reserved bits should be set to ‘0’ during set control register commands
0 = Synchronous Burst Mode
1 = Asynchronous Mode (Default)
0 = Variable (Default)
1 = Fixed
DQ1
3
A13
13
DQ1
2
A12
12
DQ1
1
A11
11
DQ1
0
A10
10
DQ
9
A9
9
128-Mbit W18 Family with Synchronous PSRAM
Description
DQ
8
A8
8
DQ
7
A7
7
DQ
6
A6
6
DQ
5
A5
5
DQ
4
Order Number: 311760-10
A4
4
DQ
3
A3
3
November 2007
DQ
2
A2
2
DQ
1
1
A1
DQ
0
A0
0

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