RD38F2240WWYTQ0SB93 Micron Technology Inc, RD38F2240WWYTQ0SB93 Datasheet - Page 41

• Manufacturer Part Number: RD38F2240WWYTQ0SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWYTQ0SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
Figure 26: Example of the Latency of First Valid Data in Synchronous Mode
9.3.1.4
9.3.1.5
9.3.1.6
9.3.1.7
9.3.1.8
November 2007
Order Number: 311760-10
PSRAM WAIT Polarity BCR Bit
The WAIT polarity control bit allows the user to define the polarity of the WAIT output
signal. The WAIT output line is used during a variable latency synchronous read burst
to signal when the output data is invalid. Active low WAIT polarity means that when
WAIT is asserted low, output data is invalid. Similarly active high WAIT polarity means
that when WAIT is asserted high, output data is invalid.
PSRAM WAIT Configuration BCR Bit
The WAIT signal configuration control bit specifies whether the WAIT signal is asserted
at the time of the delay or whether it is asserted one clock cycle in advance of the
delay.
PSRAM Drive Strength BCR Bit
For adaptation to different system characteristics the output impedance can be
configured. Full drive strength is targeted for 25-30 Ohm systems, half drive strength is
targeted for 50 Ohm systems, and quarter drive strength is targeted for 100 Ohm
systems.
PSRAM Burst Wrap BCR Bit
The burst wrap control bit defines whether there is a wrap around within a burst access
or not. In case of fixed 8-word burst length, this means that after word #7, word #0 is
going to be output in wrap mode.
In case of continuous burst mode the internal address counter will increment
continuously until terminated by the system.
mode, the burst access must be terminated prior to a row boundary crossing.
The burst wrap setting is used for both Write and Read operations.
PSRAM Burst Length BCR Bit
The burst length setting defines the Wrap boundary whenever Burst Wrap is enabled by
setting BCR3 = 0b. When Burst Wrap is disabled by setting BCR3 = 1b, all burst behave
as Continuous Bursts regardless of the Burst Length setting. Furthermore all fixed
length bursts (4-, 8-, 16-, and 32-word bursts) will continue until terminated by
bringing CE# high or interrupted by initiating a new burst access. Continuous Burst and
For continuous burst mode or non-wrap
Datasheet
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