PIC18F44K20-E/MV Microchip Technology, PIC18F44K20-E/MV Datasheet - Page 360

• Manufacturer Part Number: PIC18F44K20-E/MV
• Description: 16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F44K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC18F2XK20/4XK20
MOVSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (dest.)
Description
Words:
Cycles:
Example:
DS41303G-page 360
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
Contents
of 86h
FSR2
Contents
of 85h
Contents
of 86h
Q1
source addr
Determine
Determine
dest addr
Move Indexed to Indexed
MOVSS [z
0  z
0  z
((FSR2) + z
None
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a
2
2
MOVSS [05h], [06h]
1110
1111
Q2
=
=
=
=
=
=
s
d
 127
 127
80h
33h
11h
80h
33h
33h
s
s
1011
xxxx
], [z
)  ((FSR2) + z
source addr
Determine
Determine
dest addr
d
Q3
]
s
’ or ‘z
1zzz
xzzz
d
’,
source reg
to dest reg
NOP
d
)
Read
Write
Q4
zzzz
zzzz
.
s
d
PUSHL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2H:FSR2L
Memory (01ECh)
FSR2H:FSR2L
Memory (01ECh)
Q1
Store Literal at FSR2, Decrement FSR2
PUSHL k
0k  255
k  (FSR2),
FSR2 – 1  FSR2
None
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
1
1
1111
PUSHL 08h
Read ‘k’
Q2
 2010 Microchip Technology Inc.
1010
=
=
=
=
Process
data
Q3
01ECh
01EBh
00h
08h
kkkk
destination
Write to
kkkk
Q4