PIC18F44K20-E/MV Microchip Technology, PIC18F44K20-E/MV Datasheet - Page 277

• Manufacturer Part Number: PIC18F44K20-E/MV
• Description: 16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F44K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

TABLE 19-2:
 2010 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
ANSEL
ANSELH
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(4)
2:
3:
4:
(4)
(4)
These bits are unimplemented on PIC18F2XK20 devices; always maintain these bits clear.
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers are not implemented on PIC18F2XK20 devices.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register, High Byte
A/D Result Register, Low Byte
TRISA7
PSPIF
PSPIE
PSPIP
OSCFIF
OSCFIE
OSCFIP
ANS7
ADFM
RA7
Bit 7
RB7
IBF
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(2)
(1)
(1)
(1)
(1)
(2)
TRISA6
ANS6
RA6
ADIE
ADIP
ADIF
C1IE
C1IP
Bit 6
C1IF
RB6
OBF
—
—
—
—
—
—
(2)
(1)
(2)
PORTA Data Direction Control Register
ANS5
VCFG1
ACQT2
CHS3
RCIE
RCIP
IBOV
RCIF
C2IE
C2IP
Bit 5
C2IF
RA5
RB5
—
—
—
(1)
PSPMODE
VCFG0
ACQT1
INT0IE
ANS12
CHS2
ANS4
TXIE
TXIP
EEIF
EEIE
EEIP
Bit 4
TXIF
RA4
RB4
—
—
ACQT0
ANS11
SSPIE
SSPIP
RE3
SSPIF
BCLIF
BCLIE
BCLIP
CHS1
ANS3
PIC18F2XK20/4XK20
RBIE
Bit 3
RA3
RB3
—
—
—
(3)
PORTE Data Latch Register
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIE
HLVDIP
HLVDIF
TRISE2
ADCS2
ANS10
CHS0
ANS2
Bit 2
RA2
RB2
RE2
—
GO/DONE
TMR2IE
TMR2IP
TMR3IE
TMR3IP
TMR2IF
TMR3IF
TRISE1
ADCS1
INT0IF
ANS1
ANS9
Bit 1
RA1
RB1
RE1
—
TMR1IE
TMR1IP
TMR1IF
CCP2IF
CCP2IE
CCP2IP
TRISE0
ADCS0
ADON
ANS0
ANS8
DS41303G-page 277
Bit 0
RBIF
RA0
RB0
RE0
—
on page
Values
Reset
59
62
62
62
62
62
62
61
61
61
61
61
62
62
62
62
62
62
62
62
62
62