PIC18F44K20-E/MV Microchip Technology, PIC18F44K20-E/MV Datasheet - Page 122

• Manufacturer Part Number: PIC18F44K20-E/MV
• Description: 16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F44K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC18F2XK20/4XK20
TABLE 10-1:
DS41303G-page 122
RA0/AN0/C12IN0-
RA1/AN1/C12IN1-
RA2/AN2/C2IN+
V
RA3/AN3/C1IN+/
V
RA4/T0CKI/C1OUT
RA5/AN4/SS/
HLVDIN/C2OUT
OSC2/CLKOUT/
RA6
Legend:
REF
REF
-/CV
+
Pin
REF
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTA I/O SUMMARY
Function
CLKOUT
C12IN0-
C12IN1-
HLVDIN
C1OUT
C2OUT
C2IN+
CV
C1IN+
V
T0CKI
OSC2
V
RA0
RA1
AN0
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
REF
REF
SS
REF
+
-
Setting
TRIS
0
1
1
1
0
1
1
1
0
1
1
1
1
x
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
TTL
DIG
I/O
ST
ST
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
ADC input channel 0. Default input configuration on POR; does not
affect digital output.
Comparators C1 and C2 inverting input, channel 0. Analog select is
shared with ADC.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
ADC input channel 1. Default input configuration on POR; does not
affect digital output.
Comparators C1 and C2 inverting input, channel 1. Analog select is
shared with ADC.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
ADC input channel 2. Default input configuration on POR; not affected
by analog output.
Comparator C2 non-inverting input. Analog selection is shared with
ADC.
ADC and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
Comparator C1 non-inverting input. Analog selection is shared with
ADC.
ADC and comparator voltage reference high input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
Comparator 1 output; takes priority over port data.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
Slave select input for SSP (MSSP module).
Low-Voltage Detect external trip point input.
Comparator 2 output; takes priority over port data.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
modes.
REF
output enabled.
REF
output enabled.
OSC
Description
/4) in RC, INTIO1 and EC Oscillator
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