PIC18F44K20-E/MV Microchip Technology, PIC18F44K20-E/MV Datasheet - Page 309

• Manufacturer Part Number: PIC18F44K20-E/MV
• Description: 16KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F44K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

23.2.1
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER
TABLE 23-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
RCON
WDTCON
CONFIG2H
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
Name
U-0
—
CONTROL REGISTER
Unimplemented: Read as ‘0’
SWDTEN: Software Enable or Disable the Watchdog Timer bit
1 = WDT is turned on
0 = WDT is turned off (Reset value)
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
U-0
—
SBOREN
Bit 6
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Bit 5
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
U-0
—
Bit 4
RI
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
PIC18F2XK20/4XK20
U-0
TO
—
—
Bit 2
PD
—
(1)
U-0
—
Bit 1
POR
—
x = Bit is unknown
U-0
—
SWDTEN
WDTEN
Bit 0
BOR
DS41303G-page 309
SWDTEN
R/W-0
on page
Values
Reset
302
58
60
bit 0
(1)