PIC16F1937-E/MV Microchip Technology, PIC16F1937-E/MV Datasheet - Page 285

• Manufacturer Part Number: PIC16F1937-E/MV
• Description: 14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 14 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

24.7
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register
When a write occurs to SSPBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 24-40:
TABLE 24-4:
 2008-2011 Microchip Technology Inc.
Note 1:
Note: Values of 0x00, 0x01 and 0x02 are not valid
Baud Rate Generator
for SSPADD when used as a Baud Rate
Generator for I
limitation.
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
F
OSC
2
C interface does not conform to the 400 kHz I
MSSP CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C. This is an implementation
SSPM<3:0>
Figure 24-39
SCL
2
C and SPI Master
(Register
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
SSPM<3:0>
F
triggers the
CY
Control
Reload
24-6).
SSPCLK
Reload
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 24-4
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 24-1:
2
C specification (which applies to rates greater than
BRG Down Counter
SSPADD<7:0>
BRG Value
PIC16(L)F1934/6/7
0Ch
4Fh
13h
19h
09h
27h
09h
F
CLOCK
demonstrates clock rates based on
=
-------------------------------------------------

SSPxADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
400 kHz
400 kHz
DS41364E-page 285
308 kHz
100 kHz
308 kHz
100 kHz
100 kHz
F
+
CLOCK
1
 4  
(1)
(1)