PIC16F1937-E/MV Microchip Technology, PIC16F1937-E/MV Datasheet - Page 254

• Manufacturer Part Number: PIC16F1937-E/MV
• Description: 14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 14 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC16(L)F1934/6/7
24.4.9
The 9th SCL pulse for any transferred byte in I
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPCON2 regis-
ter is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set
when a byte is received.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the
SSPCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
DS41364E-page 254
ACKNOWLEDGE SEQUENCE
2
C is
24.5
The MSSP Slave mode operates in one of four modes
selected in the SSPM bits of SSPCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPIF additionally get-
ting set upon detection of a Start, Restart, or Stop
condition.
24.5.1
The SSPADD register
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an inter-
rupt is generated. If the value does not match, the
module goes Idle and no indication is given to the soft-
ware that anything happened.
The SSP Mask register
address matching process. See
Mask Register”
24.5.1.1
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
24.5.1.2
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPADD. Even if there is not an address match;
SSPIF and UA are set, and SCL is held low until
SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
I
2
C
I
SLAVE MODE ADDRESSES
2
C Slave 7-bit Addressing Mode
Slave Mode Operation
I
2
C Slave 10-bit Addressing Mode
for more information.
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(Register
(Register
Section 24.5.9 “SSP
24-6) contains the
24-5) affects the