PIC16F1937-E/MV Microchip Technology, PIC16F1937-E/MV Datasheet - Page 264

• Manufacturer Part Number: PIC16F1937-E/MV
• Description: 14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 14 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC16(L)F1934/6/7
24.5.4
This section describes a standard sequence of events
for the MSSP module configured as an I
10-bit Addressing mode.
Figure 24-19
description.
This is a step by step process of what must be done by
slave software to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPIF.
11. Slave reads the received matching address
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
14. If SEN bit of SSPCON2 is set, CKP is cleared by
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
17. If SEN is set the slave sets CKP to release the
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41364E-page 264
Note: Updates to the SSPADD register are not
Note: If the low address does not match, SSPIF
Bus starts Idle.
Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
Slave sends ACK and SSPIF is set.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
Slave loads low address into SSPADD,
releasing SCL.
Master sends matching low address byte to the
Slave; UA bit is set.
Slave sends ACK and SSPIF is set.
from SSPBUF clearing BF.
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
hardware and the clock is stretched.
clearing BF.
SCL.
allowed until after the ACK sequence.
and UA are still set so that the slave soft-
ware can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
SLAVE MODE 10-BIT ADDRESS
RECEPTION
is used as a visual reference for this
2
C communication.
2
C Slave in
24.5.5
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same.
slave in 10-bit addressing with AHEN set.
Figure 24-21
transmitter in 10-bit Addressing mode.
Figure 24-20
10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
shows a standard waveform for a slave
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can be used as a reference of a