DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 85

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DP83932CVF25

Manufacturer Part Number
DP83932CVF25
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83932CVF25

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Mounting
Surface Mount
Pin Count
132
Lead Free Status / RoHS Status
Not Compliant
Number
T45a
T51a
T52
T53
T54
T54a
T54b
T55
T55b
7 0 AC and DC Specifications
BUS REQUEST TIMING BMODE
Note 1 BGACK is asserted one bus clock after all the signals (AS DSACK0 1 BGACK STERM (Extended bus mode) and BG) meet the T45a setup time (see
Section 5 4 1 for more information) The address bus AS DS ECS MRW USR
Note 2 S
k
2 0
l
BG AS BGACK DSACK0 1 and STERM
Asynchronous Setup Time to BSCK (Note 1)
BSCK to Address AS MRW DS ECS
USR
BSCK to Data TRI-STATE
BSCK to Address AS MRW DS ECS
USR
BSCK Low to BR Low TRI-STATE
BSCK High to BGACK Low High
BSCK High to BGACK TRI-STATE
BSCK to Bus Status Valid
S
will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation
k
2 0
k
k
l
1 0
1 0
Hold from BSCK
l
l
and EXUSR
and EXUSR
Parameter
e
1
k
k
3 0
3 0
l
l
TRI-STATE
Active (Note 1)
(Continued)
85
k
1 0
Min
7
3
l
20 MHz
and EXUSR
Max
34
34
34
23
24
19
29
k
3 0
l
Min
6
3
will also be driven active on the same clock
25 MHz
Max
32
32
32
21
22
17
27
Min
5
3
33 MHz
Max
30
30
30
19
20
15
25
TL F 10492 – 68
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns

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