DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 71

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

6 0 Network Interfacing
Note 1 The OSCOUT pin is not guaranteed to provide a TTL compatible
Note 2 The frequency marked on the crystal is usually measured with a
6 1 3 2 Clock Oscillator Module
The SONIC also allows for an external clock oscillator to be
used The connection configuration is shown in Figure 6 5
This connection requires an oscillator with the following
specifications
1 TTL or CMOS output with a 0 01% frequency tolerance
2 40% –60% duty cycle (50% duty cycle preferred)
3 One CMOS loads output drive
The above assumes no other circuitry is driven In this con-
figuration the OSCOUT pin must be left open
FIGURE 6 5 Oscillator Module Connection to the SONIC
FIGURE 6 4 Crystal Connection to the SONIC (see text)
Resonant frequency
Tolerance (see text)
Accuracy
Fundamental Mode
Specified Load
Type
Circuit
Series Resistance
Capacitance
logic output and should not be used to drive any external logic If
additional logic needs to be driven then an external oscillator
should be used as described in the following section
fixed load capacitance specified in the crystal’s data sheet The
actual load capacitance used should be the specified value minus
the stray capacitance
TABLE 6-1 Crystal Specifications
0 005% (50 ppm) at 0 to 70 C
Parallel Resonance
(Continued)
0 01% at 25 C
TL F 10492– 81
TL F 10492– 83
20 MHz
s
AT cut
s
18 pF
25
71
6 1 3 3 PCB Layout Considerations
Care should be taken when connecting a crystal Stray ca-
pacitance (e g from PC board traces and plated through
holes around the OSCIN and OSCOUT pins) can shift the
crystal’s frequency out of range causing the transmitted fre-
quency to exceed the 0 01% tolerance specified by IEEE
The layout considerations for using an external crystal are
rather straightforward The oscillator layout should locate all
components close to the OSCIN and OSCOUT pins and
should use short traces that avoid excess capacitance and
inductance A solid ground should be used to connect the
ground legs of the two capacitors
When connecting an external oscillator the only considera-
tions are to keep the oscillator module as close to the
SONIC as possible to reduce stray capacitance and induc-
tance and to give the module a clean V
ground
6 1 4 Power Supply Considerations
In general power supply routing and design for the SONIC
need only follow standard practices In some situations
however additional care may be necessary in the layout of
the analog supply Specifically special care may be needed
for the TXVCC RXVCC and PLLVCC power supplies and
the TXGND and ANGND In most cases the analog and
digital power supplies can be interconnected However to
ensure optimum performance of the SONIC’s analog func-
tions power supply noise should be minimized To reduce
analog supply noise any of several techniques can be used
1 Route analog supplies as a separate set of traces or
2 Provide noise filtering on the analog supply pins by insert-
3 Utilize a separate regulator to generate the analog sup-
The PLLV
loop (PLL) of the SONIC ENDEC unit Since this is an ana-
log circuit excessive noise on the PLLV
the performance of the PLL This noise if in the 10 kHz to
400 kHz range can reduce the jitter performance of the
ENDEC resulting in missing packets or CRC errors If the
power supply noise is causing significant packet reception
error a low pass filter could be added to reduce the power
supply noise and hence improve the jitter performance
Standard analog design techniques should be utilized when
laying out the power supply traces on the board If the digital
power supply is used it may be desirable to add a one pole
RC filter (designed to have a cut-off frequency of 1 kHz) as
shown in Figure 6 6 to improve the jitter performance The
PLLV
resistor is less than 90 mV which will not affect the PLL’s
operation
planes from the digital supplies with their own decoupling
capacitors
ing a low pass filter Alternatively a ferrite bead could be
used to reduce high frequency power supply noise
ply
CC
FIGURE 6 6 Filtering the Power Supply Noise
only draws 3 mA– 4 mA so the voltage across the
CC
pin is the
a
5V power supply for the phase lock
CC
CC
pin can affect
and a solid
TL F 10492 – 87