DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 40

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

4 0 SONIC Registers
4 3 8 Transmit Registers
The transmit registers described in this section are part of
the User Register set The UTDA and CTDA must be initial-
ized prior to issuing the transmit command (setting the TXP
bit) in the Command register
Upper Transmit Descriptor Address Register (UTDA)
This register contains the upper address bits (A
for accessing the transmit descriptor area (TDA) and is con-
catenated with the contents of the CTDA when the SONIC
accesses the TDA in system memory The TDA can be as
large as 32k words or 16k long words and can be located
anywhere in system memory This register is unaffected by
a hardware or software reset
Current Transmit Descriptor Address Register (CTDA)
The 16-bit CTDA register contains the lower address bits
(A
initialization this register must be programmed with the low-
er address bits of the transmit descriptor The SONIC con-
catenates the contents of this register with the contents of
the UTDA to point to the transmit descriptor For 32-bit
memory systems bit 1 corresponding to address signal A1
must be set to ‘‘0’’ for alignment to long-word boundaries
Bit 0 of this register is the End of List (EOL) bit and is used
to denote the end of the list This register is unaffected by a
hardware or software reset
4 3 9 Receive Registers
The receive registers described in this section are part of
the User Register set A software reset has no effect on
these registers and a hardware reset only affects the EOBC
and RSC registers The receive registers must be initialized
prior to issuing the receive command (setting the RXEN bit)
in the Command register
Upper Receive Descriptor Address Register (URDA)
This register contains the upper address bits (A
for accessing the receive descriptor area (RDA) and is con-
catenated with the contents of the CRDA when the SONIC
accesses the RDA in system memory The RDA can be as
large as 32k words or 16k long words and can be located
anywhere in system memory This register is unaffected by
a hardware or software reset
Current Receive Descriptor Address Register (CRDA)
The CRDA is a 16-bit read write register used to locate the
received packet descriptor block within the RDA It contains
the lower address bits (A
nates the contents of the CRDA with the contents of the
URDA to form the complete 32-bit address The resulting
32-bit address points to the first field of the descriptor block
For 32-bit memory systems bit 1 corresponding to address
signal A1 must be set to ‘‘0’’ for alignment to long-word
boundaries Bit 0 of this register is the End of List (EOL) bit
and is used to denote the end of the list This register is
unaffected by a hardware or software reset
End of Buffer Word Count Register (EOBC) The SONIC
uses the contents of this register to determine where to
place the next packet At the end of packet reception the
SONIC compares the contents of the EOBC register with
the contents of the Remaining Buffer Word Count registers
(RBWC0 1) to determine whether (1) to place the next
packet in the same RBA or (2) to place the next packet in
another RBA If the EOBC is less than or equal to the re-
maining number of words in the RBA after a packet is re-
ceived (i e EOB
packet in the same RBA If the EOBC is greater than
k
15 1
l
) of the 32-bit transmit descriptor address During
s
RBWC0 1) the SONIC buffers the next
k
15 1
l
(Continued)
) The SONIC concate-
k
k
31 16
31 16
l
l
)
)
40
the remaining number of words in the RBA after a packet is
received (i e EOBC
bit LPKT in the Receive Control Register Section 4 3 3 is
set and the SONIC fetches the next resource descriptor
Hence the next packet received will be buffered in a new
RBA A hardware reset sets this register to 02F8H (760
words or 1520 bytes) See Sections 3 4 2 and 3 4 4 4 for
more information about using EOBC
Upper Receive Resource Address Register (URRA) The
URRA is a 16-bit read write register It is programmed with
the base address of the receive resource area (RRA) This
16-bit upper address value (A
resource area in system memory SONIC uses the URRA
register when accessing the receive descriptors within the
RRA by concatenating the lower address value from one of
four receive resource registers (RSA REA RWP or RRP)
Resource Start Address Register (RSA) The RSA is a
15-bit read write register The LSB is not used and always
reads back as a 0 The RSA is programmed with the lower
15-bits (A
resource area SONIC concatenates the contents of this
register with the contents of the URRA to form the complete
32-bit address
Resource End Address Register (REA) The REA is a
15-bit read write register The LSB is not used and always
reads back as a 0 The REA is programmed with the lower
15-bits (A
source area SONIC concatenates the contents of this reg-
ister with the contents of the URRA to form the complete
32-bit address
Resource Read Pointer Register (RRP) The RRP is a
15-bit read write register The LSB is not used and always
reads back as a 0 The RRP is programmed with the lower
15-bit address (A
scriptor the SONIC will read SONIC concatenates the con-
tents of this register with the contents of the URRA to form
the complete 32-bit address
Resource Write Pointer Register (RWP) The RWP is a
15-bit read write register The LSB is not used and always
reads back as a 0 The RWP is programmed with the lower
15-bit address (A
system can add a descriptor SONIC concatenates the con-
tents of this register with the contents of the URRA to form
the complete 32-bit address In 32-bit mode bit 1 corre-
sponding to address signal A1 must be zero to insure the
proper equality comparison between this register and the
RRP register
Receive Sequence Counter Register (RSC) This is a
16-bit read write register containing two fields The SONIC
uses this register to provide status information on the num-
ber of packets within a RBA and the number of RBAs The
RSC register contains two 8-bit (modulo 256) counters Af-
ter each packet is received the packet sequence number is
incremented The SONIC maintains a single sequence num-
ber for each RBA When the SONIC uses the next RBA the
packet sequence number is reset to zero and the RBA se-
quence number is incremented This register is reset to 0 by
a hardware reset or by writing zero to it A software reset
has no affect
15
RBA Sequence Number
(Modulo 256)
k
k
15 1
15 1
l
l
k
k
) of the ending address of the receive re-
) of the starting address of the receive
15 1
15 1
l
l
RBWC0 1) the Last Packet in RBA
l
8
) of the next available location the
) of the first field of the next de-
k
7
Packet Sequence Number
31 16
(Modulo 256)
l
) locates the receive
0