DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 35

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

4 0 SONIC Registers
4 3 5 Interrupt Mask Register
(RA
This register masks the interrupts that can be generated from the ISR (Figure 4–8) Writing a ‘‘1’’ to the bit enables the
corresponding interrupt During a hardware reset all mask bits are cleared
r w
15
Bit
0 BREN HBLEN LCDEN PINTEN PRXEN PTXEN TXEREN TCEN RDEEN RBEEN RBAEEN CRCEN FAEEN MPEN RFOEN
15
14
13
12
11
10
9
8
e
k
read write
r w
14
5 0
l
Must be 0
BREN BUS RETRY OCCURRED enabled
0 disable
1 enables interrupts when a Bus Retry operation is requested
HBLEN HEARTBEAT LOST enable
0 disable
1 enables interrupts when a heartbeat lost condition occurs
LCDEN LOAD CAM DONE INTERRUPT enable
0 disable
1 enables interrupts when the Load CAM command has finished
PINTEN PROGRAMMABLE INTERRUPT enable
0 disable
1 enables programmable interrupts to occur when the PINT bit the TXpkt config field is set to a ‘‘1’’
PRXEN PACKET RECEIVED enable
0 disable
1 enables interrupts for packets accepted
PTXEN PACKET TRANSMITTED OK enable
0 disable
1 enables interrupts for transmit completions
TXEREN TRANSMIT ERROR enable
0 disable
1 enables interrupts for packets transmitted with error
e
r w
13
4h)
r w
12
r w
11
BREN
HBLEN
LCDEN
PINTEN
PRXEN
PTXEN
TXEREN
TCEN
RDEEN
RBEEN
RBAEEN
CRCEN
FAEEN
MPEN
RFOEN
(Continued)
Field
r w
10
FIGURE 4-8 Interrupt Mask Register
r w
BUS RETRY OCCURRED ENABLE
HEARTBEAT LOST ENABLE
LOAD CAM DONE INTERRUPT ENABLE
PROGRAMMABLE INTERRUPT ENABLE
PACKET RECEIVED ENABLE
PACKET TRANSMITTED OK ENABLE
TRANSMIT ERROR ENABLE
TIMER COMPLETE ENABLE
RECEIVE DESCRIPTORS ENABLE
RECEIVE BUFFERS EXHAUSTED ENABLE
RECEIVE BUFFER AREA EXCEEDED ENABLE
CRC TALLY COUNTER WARNING ENABLE
FAE TALLY COUNTER WARNING ENABLE
MP TALLY COUNTER WARNING ENABLE
RECEIVE FIFO OVERRUN ENABLE
9
r w
8
35
Description
r w
7
Meaning
r w
6
r w
5
r w
4
r w
3
r w
2
r w
1
r w
0