DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 59

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

5 0 Bus Interface
bus clocks after DSACK0 1 were sampled or 1 cycle after
STERM was sampled T2 states will be repeated until
DSACK0 1 or STERM are sampled properly in a low state
(see note below)
During read cycles ( Figures 5-10 and 5-11 ) data (D31-D0)
is latched at the falling edge of T2 and DS is asserted at the
falling edge of T1 For write cycles ( Figures 5-12 and 5-13 )
data is driven on the rising edge of T1 If there are wait
FIGURE 5-12 Memory Write BMODE
FIGURE 5-13 Memory Write BMODE
(Continued)
59
e
e
states inserted DS is asserted on the falling edge of the first
T2 (wait) DS is not asserted for zero wait state write cycles
The SONIC terminates the memory cycle by deasserting AS
and DS at the falling edge of T2
Note If the setup time for DSACK0 1 is met during T1 or the setup time for
1 Asynchronous (1 Wait-State)
1 Asynchronous (2 Wait-State)
STERM is met during the first T2 the full asynchronous bus cycle will
take only 2 bus clocks This may be an unwanted situation If so
DSACK0 1 and STERM should normally be deasserted during T1 and
the start of T2 respectively
TL F 10492 – 34
TL F 10492 – 35