DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 65

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

5 0 Bus Interface
5 4 7 2 Slave Cycle for BMODE
The system accesses the SONIC by driving SAS CS SWR
and RA
SAS are asserted properly SONIC samples CS asynchro-
nously at the falling edge of each BSCK SAS signal may be
asserted low anytime before or simultaneously to the falling
edge of the CS and the deassertion of SAS will start the
slave cycle CS should not be asserted low before the falling
edge of SAS as this will cause improper slave operation
The register address RA
SWR will be latched by the SONIC on the rising edge of the
SAS signal Once CS is asserted and SAS is deasserted
SMACK will be asserted by the SONIC to signify that the
SONIC has started the slave cycle Although CS and SAS
are asynchronous inputs meeting their setup times (as
shown in Figures 5-23 and 5-24 ) will guarantee that
SMACK which is asserted off a falling edge will be assert-
ed on the falling edge of the BSCK and SAS was sampled
high on This is assuming that the SONIC is not a bus mas-
ter when CS is asserted If the SONIC is a bus master then
when CS is asserted the SONIC will complete its current
master bus cycle and get off the bus temporarily (see Sec-
tion 5 4 8) In this case SMACK will be asserted maximum 4
bus clocks after the falling edge of BSCK that SAS was
sampled high on This is assuming that there were no wait
states in the current master mode access Wait states will
increase the time for SMACK to go low by the number of
wait states in the cycle
k
5 0
l
SONIC will start a slave cycle once CS and
k
5 0
(Continued)
l
e
and the read write signal
0
FIGURE 5-23 Register Read BMODE
65
If the slave access is a read cycle ( Figure 5-23 ) then the
data will be driven off the same edge as SMACK If it is a
write cycle ( Figure 5-24 ) then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK In either
case RDYo is driven low 2 5 bus clocks after SMACK to
terminate the slave cycle For a read cycle the assertion of
RDYo indicates valid register data and for a write cycle the
assertion indicates that the SONIC has latched the data
The SONIC deasserts RDYo SMACK and the data if the
cycle is a read cycle at the falling edge of SAS or the rising
edge of CS depending on which is first
Note 1 The SONIC transfers data only on lines D
Note 2 For multiple register accesses CS can be held low and SAS can be
Note 3 If memory request (MREQ) follows a chip select CS it must be
Note 4 When CS is deasserted it must remain deasserted for at least one
Note 5 The way in which SMACK is asserted due to CS is not the same as
mode accesses
used to delimit the slave cycle (this is the only case where CS may
be asserted before SAS) In this case SMACK will be driven low
due to SAS going high since CS has already been asserted Notice
that this means SMACK will not stay asserted low during the entire
time CS is low (as is the case for MREQ see Section 5 4 8)
asserted at least 2 bus clocks after CS is deasserted Both CS and
MREQ must not be asserted concurrently
bus clock
the way in which SMACK is asserted due to MREQ The assertion of
SMACK is dependent upon both CS and SAS being low not just CS
This is not the same as the case for MREQ (see Section 5 4 8) The
assertion of SMACK in these two cases should not be confused
e
0
k
15 0
l
TL F 10492 – 49
during slave