DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 48

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

BUS INTERFACE PINS (Continued)
D31 –D0
A31 –A1
RA5 –RA0
AS
ADS
MRW
MWR
INT
INT
RESET
S2 –S0
BSCK
BR
HOLD
BG
HLDA
BGACK
5 0 Bus Interface
Symbol
Driver
Type
TRI
TRI
TRI
TRI
TRI
TRI
TRI
OC
OC
TP
TP
TP
Direction
(Continued)
I O Z
I O Z
O Z
O Z
O Z
O Z
O Z
O Z
O Z
O
O
O
I
I
I
I
I
Data Bus These bidirectional lines are used to transfer data on the system bus When
the SONIC is a bus master 16-bit data is transferred on D15– D0 and 32-bit data is
transferred on D31– D0 When the SONIC is accessed as a slave register data is driven
onto lines D15–D0 D31 – D16 are held TRI-STATE if SONIC is in 16-bit mode If SONIC
is in 32-bit mode they are driven but invalid
Address Bus These signals are used by the SONIC to drive the DMA address after the
SONIC has acquired the bus Since the SONIC aligns data to word boundaries only 31
address lines are needed
Register Address Bus These signals are used to access SONIC’s internal registers
When the SONIC is accessed the CPU drives these lines to select the desired SONIC
register
Address Strobe (AS) When BMODE
address The rising edge indicates the termination of the memory cycle
Address Strobe (ADS) When BMODE
address
When the SONIC has acquired the bus this signal indicates the direction of data
Memory Read Write Strobe (MRW) When BMODE
read cycle and low during a write cycle
Memory Read Write Strobe (MWR) When BMODE
read cycle and high during a write cycle
Indicates that an interrupt (if enabled) is pending from one of the sources indicated by
the Interrupt Status register Interrupts that are disabled in the Interrupt Mask register
will not activate this signal
Interrupt (INT) This signal is active low when BMODE
Interrupt (INT) This signal is active high when BMODE
Reset This signal is used to hardware reset the SONIC When asserted low the SONIC
transitions into the reset state after 10 transmit clocks or 10 bus clocks if the bus clock
period is greater than the transmit clock period
Bus Status These three signals provide a continuous status of the current SONIC bus
operations See Section 5 4 3 for status definitions
Bus Clock This clock provides the timing for the SONIC DMA engine
Bus Request (BR) When BMODE
attempts to gain access to the bus When inactive this signal is tri-stated
Hold Request (HOLD) When BMODE
intends to use the bus and is driven low when inactive
Bus Grant (BG) When BMODE
pin low to indicate potential mastership of the bus
Hold Acknowledge (HLDA) When BMODE
SONIC that it has attained the bus When the system asserts this pin high the SONIC
has gained ownership of the bus This signal is sampled synchronously and the setup
time must be met to ensure proper operation
Bus Grant Acknowledge When BMODE
has determined that it can gain ownership of the bus The SONIC checks the following
signal before driving BGACK 1) BG has been received through the bus arbitration
process 2) AS is deasserted indicating that the CPU has finished using the bus 3)
DSACK0 and DSACK1 are deasserted indicating that the previous slave device is off
the bus 4) BGACK is deasserted indicating that the previous master is off the bus This
pin is only used when BMODE
TABLE 5-1 Pin Description (Continued)
48
e
e
1
1 this signal is a bus grant The system asserts this
e
Description
1 the SONIC asserts this pin low when it
e
e
e
1 the falling edge indicates valid status and
0 the SONIC drives this pin high when it
e
0 the rising edge indicates valid status and
e
1 the SONIC asserts this pin low when it
0 this signal is used to inform the
e
e
e
e
1 this signal is high during a
0 the signal is low during a
1
0