DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 30

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

Bits
9 8
7 6
3 2
1 0
10
5
4
4 0 SONIC Registers
4 3 2 Data Configuration Register (Continued)
SBUS SYNCHRONOUS BUS MODE
The SBUS bit is used to select the mode of system bus operation when SONIC is a bus master This bit selects the internal
ready line to be either a synchronous or asynchronous input to SONIC during block transfer DMA operations
0 Asynchronous mode RDYi (BMODE
1 Synchronous mode RDYi (BMODE
USR1 0 USER DEFINABLE PINS
The USR1 0 bits report the level of the USR1 0 signal pins respectively after a chip hardware reset If the USR1 0 signal pins
are at a logical 1 (tied to V
to ground) during a hardware reset the USR1 0 bits are set to a 0 These bits are latched on the rising edge of RST Once set
they remain set reset until the next hardware reset
WC1 0 WAIT STATE CONTROL
These encoded bits determine the number of additional bus cycles (T2 states) that are added during each DMA cycle
WC1
DW DATA WIDTH SELECT
These bits select the data path width for DMA operations
BMS BLOCK MODE SELECT FOR DMA
Determines how data is emptied or filled into the Receive or Transmit FIFO
0 Empty fill mode All DMA transfers continue until either the Receive FIFO has emptied or the Transmit FIFO has
1 Block mode All DMA transfers continue until the programmed number of bytes (RFT0 RFT1 during reception or TF0
RFT1 RFT0 RECEIVE FIFO THRESHOLD
These encoded bits determine the number of words (or long words) that are written into the receive FIFO from the MAC unit
before a receive DMA request occurs (See Section 1 4 )
Note In block mode (BMS bit
TFT1 TFT0 TRANSMIT FIFO THRESHOLD
These encoded bits determine the minimum number of words (or long words) the DMA section maintains in the transmit
FIFO A bus request occurs when the number of words drops below the transmit FIFO threshold (See Section 1 4 )
Note In block mode (BMS
or long words needed to fill the FIFO is less than the threshold value then only the number of reads required to fill the FIFO in a single DMA burst will be made
Typically with the FIFO threshold value set to 12 or 14 words the number of memory reads needed is less than the FIFO threshold value
LB1
LB1
DW
0
0
1
1
0
1
0
0
1
1
0
0
1
1
at the falling edge of the bus clock (T2 of the DMA cycle) No setup or hold times need to be met with respect to this edge
to guarantee proper bus operation The minimum memory cycle time is 3 bus clocks
hold times with respect to the rising edge of T1 or T2 to guarantee proper bus operation
filled completely
TF1 during transmission) have been transferred (See note for TFT0 TFT1 )
Data Width
16-bit
32-bit
WC0
LB0
LB0
0
1
0
1
0
1
0
1
0
1
0
1
e
12 words or 6 long words (24 bytes)
12 words or 6 long words (24 bytes)
14 words or 7 long words (28 bytes)
2 words or 1 long word (4 bytes)
4 words or 2 long words (8 bytes)
8 words or 4 long words (16 bytes)
4 words or 2 long words (8 bytes)
8 words or 4 long words (16 bytes)
1) the number of bytes the SONIC reads in a single DMA burst equals the transmit FIFO threshold value If the number of words
e
CC
1) the receive FIFO threshold sets the number of words (or long words) written to memory during a receive DMA block cycle
) during a hardware reset the USR1 0 bits are set to a 1 If the USR1 0 pins are at a logical 0 (tied
Bus Cycles Added
(Continued)
Function
Function
e
0
1
2
3
e
0) and DSACK0 1 (BMODE
0) or DSACK0 1 (BMODE
Description
30
e
e
1) are respectively internally synchronized
1) must respectively meet the setup and